Datasheet 2ED2106 (4) S06F (J) (Infineon) - 10

link to page 10 2ED2106 (4) S06F (J) 650 V high-side and low-side gate driver with integrated bootstrap diode 5.3 Matched propagation delays The 2ED2106 (4) S06F (J) is designed with propagation delay matching circuitry. With this feature, the IC’s response at the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the high-side channels; the maximum difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON) of the 2ED2106 (4) S06F (J) is matched to the propagation turn-off delay (tOFF). 50% 50% HIN LIN LO HO 10% MT MT 90% LO HO Figure 8 Delay matching waveform definition 5.4 Input logic compatibility The input pins are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc supply voltage. With typical high threshold (VIH) of 2.1 V and typical low threshold (VIL) of 0.9 V, along with very little temperature variation as summarized in Figure 9, the input pins are conveniently driven with logic level PWM control signals derived from 3.3 V and 5 V digital power-control er devices. Wider hysteresis (typical y 0.9 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. 2ED2106 (4) S06F (J) also features tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature. The 2ED2106 (4) S06F (J) features floating input protection wherein if any of the input pin is left floating, the output of the corresponding stage is held in the low state. This is achieved using pull-down resistors on all the input pins (HIN, LIN) as shown in the block diagram. The 2ED2106 (4) S06F (J) has input pins that are capable of sustaining voltages higher than the bias voltage applied on the Vcc pin of the device. Figure 9 HIN & LIN input thresholds Datasheet 10 of 24 V 2.10 www.infineon.com/soi 2019-09-12 Document Outline Features Product summary Potential applications Product validation Ordering information Description 1 Table of contents 2 Block diagram 3 Pin configuration and functionality 3.1 Pin configuration 3.2 Pin functionality 4 Electrical parameters 4.1 Absolute maximum ratings 4.2 Recommended operating conditions 4.3 Static electrical characteristics 4.4 Dynamic electrical characteristics 5 Application information and additional details 5.1 IGBT / MOSFET gate drive 5.2 Switching and timing relationships 5.3 Matched propagation delays 5.4 Input logic compatibility 5.5 Undervoltage lockout 5.6 Bootstrap diode 5.7 Calculating the bootstrap capacitance CBS 5.8 Tolerant to negative tranisents on input pins 5.9 Negative voltage transient tolerance of VS pin 5.10 NTSOA – Negative Transient Safe Operating Area 5.11 Higher headroom for input to output signal transmission with logic operation upto -11 V 5.12 Maximum switching frequency 5.13 PCB layout tips 6 Qualification information0F 7 Related products 8 Package details 9 Part marking information 10 Additional documentation and resources 10.1 Infineon online forum resources 11 Revision history