Datasheet 48L256 (Microchip) - 8

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48L256 3.0 MEMORY ORGANIZATION 3.1 Data Array Organization
The 48L256 is internally organized as a continuous SRAM array for both reading and writing, along with a nonvolatile EEPROM array that is not directly accessible to the user, but which can be refreshed or recalled on power cycles or on software commands. The array can be configured either as a continuous range or into pages. The page size in this device is 64 bytes. The Page mode option is controlled by the PRO bit in the STATUS register.
3.2 16-Bit Nonvolatile User Space
The 48L256 device contains a 16-bit (2-byte) nonvolatile user space, separate from the SRAM memory array. The nonvolatile user space can be written with the Write Nonvolatile User Space command and read with the Read Nonvolatile User Space command. Once written, these 2 bytes remain volatile and can be rewritten. They are copied to nonvolatile memory – at the same time as the SRAM array and STATUS register – automatically on any power disruption or by using the Software Store command described in
Section 11.0 “Store/Recall Operations”
. Reading and writing to the nonvolatile user space does not use address bits, only the specific access instruction to precede the operation. Writing to the nonvolatile user space requires writing all of its bits in one operation. Failing to write to all nonvolatile user space bits wil abort the write operation and leave the nonvolatile user space value unchanged from its previous value. Similarly, reading the nonvolatile user space memory uses no address bits, but partial reads are allowed.
3.3 Device Registers
The 48L256 contains a STATUS register for controlling and monitoring functions of the device. 3.3.1 STATUS REGISTER The STATUS register is an 8-bit combination of writable and read-only bits. It is used to modify the write protection functions as well as store various aspects of the current status of the device. The writable bit values written to the STATUS register are volatile – until they are copied to nonvolatile memory automatically on any power disruption or by using the Software Store command described in
Section 11.0 “Store/Recall Operations”
– and can be overwritten from a previous status in a recal operation. Details about the STATUS register are covered in
Section 6.0 “STATUS Register”
.  2019 Microchip Technology Inc.
Preliminary
DS20006237B-page 8 Document Outline Serial SRAM Features Hidden EEPROM Backup Features Other Features of the 48L256 Packages Package Types (not to scale) Pin Function Table General Description Block Diagram Normal Device Operation Vcc Power-Off Event 1.0 Electrical Characteristics Absolute Maximum Ratings† TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics TABLE 1-3: AC Test Conditions 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 Chip Select (CS) 2.2 Serial Output (SO) 2.3 Serial Input (SI) 2.4 Serial Clock (SCK) 2.5 Hold (HOLD) 3.0 Memory Organization 3.1 Data Array Organization 3.2 16-Bit Nonvolatile User Space 3.3 Device Registers 3.3.1 STATUS Register 4.0 Functional Description FIGURE 4-1: SPI Mode 0 and Mode 3 4.1 Interfacing the 48L256 on the SPI Bus 4.1.1 Selecting the Device 4.1.2 Sending Data to the Device 4.1.3 Receiving Data from the Device 4.2 Device Opcodes 4.2.1 Serial Opcode 4.2.2 Hold Function FIGURE 4-2: Hold Mode 5.0 Write Enable and Disable 5.1 Write Enable Instruction (WREN) FIGURE 5-1: WREN Waveform 5.2 Write Disable Instruction (WRDI) FIGURE 5-2: WRDI Waveform 6.0 STATUS Register 6.1 Block Write-Protect Bits TABLE 6-2: Block Write-Protect Bits 6.2 Write Enable Latch 6.3 Ready/Busy Status Latch 6.4 Read STATUS Register (RDSR) FIGURE 6-1: RDSR Waveform 6.5 Write STATUS Register (WRSR) FIGURE 6-2: WRSR Waveform 7.0 Read Operations 7.1 Reading from the SRAM (READ) FIGURE 7-1: Read SRAM (READ) Waveform 7.2 Read Last Successfully Written Address (RDLSWA) FIGURE 7-2: Read Last Successfully Written Address Waveform 8.0 Write Commands 8.1 Write Instruction Sequences 8.1.1 SRAM Byte Write FIGURE 8-1: SRAM Byte Write Waveform 8.1.2 Continuous Write FIGURE 8-2: Continuous SRAM Write Waveform 9.0 Nonvolatile User Space Access 9.1 Write Nonvolatile User Space (WRNUR) 9.2 Read Nonvolatile User Space (RDNUR) 10.0 Secure Operations 10.1 Secure Write 10.2 Secure Read TABLE 10-1: Secure Write Bits 11.0 Store/Recall Operations 11.1 Automatic Store on Any Power Disruption 11.2 Automatic Recall to SRAM 11.3 Software Store Command FIGURE 11-1: Software Store 11.4 Software Recall Command FIGURE 11-2: Software Recall 11.5 Polling Routine FIGURE 11-3: Polling Flow 12.0 Hibernation FIGURE 12-1: Hibernate Waveform 13.0 Trip Voltage 13.1 Power Switchover 14.0 Packaging Information 14.1 Package Marking Information Appendix A: Revision History Product ID System Trademarks Worldwide Sales and Service