Data Brief AK8464 (Asahi Kasei Microdevices) - 7

Product Brief
[AK8464]  TG(Timing Generator), LINE_CTRL1: Timing Generation Circuit This block generates sensor drive pulse and line control pulse from pixel cycle clock <PCLK>. with CCD Sensor Sensor drive pulses, <P0~2>, <PRS> and <PCL>, are generated based on <PCLK> clock. Internal drive pulses, <SHD> and <SHR>, are generated based on <PCLK> clock. Stop period of sensor drive pulse, vertical transmission period, <SH0> ~ <SH6> and general-purpose signal <PWM> are generated based on <PCLK> clock and the TRIG pin. <AGC_EN>, <OBP>, <SHR_EN>, <SH> and <EN> are generated based on <PCLK> clock and the TRIG pin. with CIS Sensor Sensor drive pulse <CISCK> is generated based on <PCLK> clock. Internal drive pulse <SHD> is generated based on <PCLK> clock. Sensor reference signal <SP1> and <SP2>, stop period of sensor drive pulse, and LED control pulse <LED0 ~ 5> and <LED_EN> are generated based on <PCLK> clock and the TRIG pin. Three LED lighting modes, MAN, RGB1 and RGB2, are supported. <BOS>, <STA>, <CL0>, <CL1> and <EN> are generated based on PLCK clock and the TRIG pin. Rising and falling edges of <P0~2>, <PRS>, <PCL>, <SHD>, <SHR>, <CISCK> and the TRIG pin can be set in 1/56 phase of one pixel cycle by referring a rising edge of <PCLK> clock as 0 phase. <SH0> ~ <SH6>, <PWM>, <SP1>, <SP2>, <LED0 ~ 5> and <LED_EN> change on a rising edge (0 phase) of <PCLK> clock in pixel cycle.  OSC+SYNTH: Pixel Cycle clock generator Pixel cycle clock is generated by multiplying an external input clock or crystal oscillator signal by 1~1.57 times. When an external SS clock is input, this block is bypassed and clock frequency of the input clock will be the pixel cycle.  SSCG_PLL: SS clock generator Generate spread spectrum clock. The SS clock has 30kHz ~ 50kHz modulation cycle and 0.43 ~ 2.08% modulation width. SS clock generation can also be set ON/OFF setting of is also available. When inputting external SS clock, this SS clock generator should be OFF.  DLL: ADC Operation clock generation Circuit ADC operational clock is generated from <SHD> by this DLL circuit.  Serial I/F: Control Register, Interface Circuit This block is a 4-wire serial interface to access control registers. Control register settings can also be readout. When PORT0/1 is input mode, input signal polarity of PORT0/1 can be read by register value. When PORT0/1 is output mode, the output signal polarity can be set by register setting.  LDO: Low Voltage Power Supply block LDOA generates 1.8V internal power from 3.3V input to the AVDD33, LDOS, LDODSS0, LDODSS1 and SDVDD33 pins. The AK8464 has three LDOs for the ADC, GIG, TG, LVDS, SYNTH_PLL and SSCG_PLL blocks. Rev.1.00E 2019/6 - 7 -