Datasheet MTD20P06HDL (Motorola)

Order this document SEMICONDUCTOR TECHNICAL DATA by MTD20P06HDL/D
  !
Motorola Preferred Device TMOS POWER FET P–Channel Enhancement–Mode Silicon Gate LOGIC LEVEL 15 AMPERES
This advanced high–cell density HDTMOS E–FET is designed to
60 VOLTS
withstand high energy in the avalanche and commutation modes.
RDS(on) = 175 M
Ω The new energy efficient design also offers a drain–to–source diode with a fast recovery time. Designed for low–voltage, high–speed switching applications in power supplies, converters  and PWM motor controls, and other inductive loads. The avalanche energy capability is specified to eliminate the guesswork in designs where inductive loads are switched, and to offer additional safety margin against unexpected voltage transients. D • Ultra Low RDS(on), High–Cell Density, HDTMOS • Diode is Characterized for Use in Bridge Circuits • IDSS and VDS(on) Specified at Elevated Temperature • G Avalanche Energy Specified
CASE 369A–13, Style 2
• Surface Mount Package Available in 16 mm, 13–inch/2500
DPAK
Unit, Tape & Reel, Add T4 Suffix to Part Number S
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating Symbol Value Unit
Drain–Source Voltage VDSS 60 Vdc Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 60 Vdc Gate–Source Voltage — Continuous VGS ± 15 Vdc Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGSM ± 20 Vpk Drain Current — Continuous ID 15 Adc Drain Current — Continuous @ 100°C ID 9.0 Drain Current — Single Pulse (tp ≤ 10 µs) IDM 45 Apk Total Power Dissipation PD 72 Watts Derate above 25°C 0.58 W/°C Total Power Dissipation @ TC = 25°C (1) 1.75 Watts Operating and Storage Temperature Range TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 300 mJ (VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 15 Apk, L = 2.7 mH, RG = 25 Ω) Thermal Resistance — Junction to Case RθJC 1.73 °C/W Thermal Resistance — Junction to Ambient RθJA 100 Thermal Resistance — Junction to Ambient (1) RθJA 71.4 Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C (1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. Designer’s, E–FET and HDTMOS are trademarks of Motorola Inc. TMOS is a registered trademark of Motorola Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
REV 1
Motorola TMOS Power MOSFET Transistor Device Data 1 Motorola, Inc. 1995