Datasheet MAX517, MAX518, MAX519 (Maxim) - 8
| Hersteller | Maxim |
| Beschreibung | 2-Wire, Serial, 8-Bit DACs with Rail-to-Rail Outputs |
| Seiten / Seite | 16 / 8 — 2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs. MAX517/MAX518/MAX519. … |
| Dateiformat / Größe | PDF / 1.2 Mb |
| Dokumentensprache | Englisch |
2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs. MAX517/MAX518/MAX519. The START and STOP Conditions. The Slave Address
Modelllinie für dieses Datenblatt
- MAX517ACPA MAX517ACPA+ MAX517ACSA MAX517ACSA+ MAX517ACSA+T MAX517AEPA MAX517AEPA+ MAX517AESA MAX517AESA+ MAX517AESA+T MAX517BCPA MAX517BCPA+ MAX517BCSA MAX517BCSA+ MAX517BCSA+T MAX517BEPA MAX517BEPA+ MAX517BESA MAX517BESA+ MAX517BESA+T
Textversion des Dokuments
2-Wire Serial 8-Bit DACs with Rail-to-Rail Outputs
SDA t t BUF SU, DAT tSU, STA tHD, STA t t LOW tHD, DAT SU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 2. Two-Wire Serial Interface Timing Diagram The address byte and pairs of command and output bytes are transmitted between the START and STOP con- ditions. The SDA state is allowed to change only while SCL is low, with the exception of START and STOP condi- µC REF0 +1V tions. SDA’s state is sampled, and therefore must remain REF1 +4V DUAL stable while SCL is high. Data is transmitted in 8-bit SDA SCL
MAX517/MAX518/MAX519
DAC bytes. Nine clock cycles are required to transfer the data R bits to the MAX517/MAX518/MAX519. Set SDA low dur- C MAX519 1kΩ SCL OUT0 OFFSET ADJUSTMENT ing the 9th clock cycle as the MAX517/MAX518/MAX519 SDA pull SDA low during this time. RC (see Figure 3) limits the AD0 OUT1 GAIN ADJUSTMENT current that flows during this time if SDA stays high for AD1 short periods of time. AD2 AD3
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmis- DUAL DAC sion with a START condition by transitioning SDA from high to low while SCL is high (Figure 5). When the mas- MAX518 ter has finished communicating with the slave, it issues SCL a STOP condition by transitioning SDA from low to high SDA OUT0 BRIGHTNESS ADJUSTMENT while SCL is high. The bus is then free for another AD0 OUT1 CONTRAST ADJUSTMENT transmission. AD1
The Slave Address
REF0 +2.5V The MAX517/MAX518/MAX519 each have a 7-bit long SINGLE slave address (Figure 6). The first three bits (MSBs) of DAC the slave address have been factory programmed and MAX517 SCL are always 010. In addition, the MAX517 and MAX518 OUT0 THRESHOLD ADJUSTMENT SDA have the next two bits factory programmed to 1s. The +5V AD0 logic state of the address inputs (AD0 and AD1 on the AD1 MAX517/MAX518; AD0, AD1, AD2, and AD3 on the MAX519) determine the LSB bits of the 7-bit slave address. These input pins may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels. The MAX517/MAX518 have four possible Figure 3. MAX517/MAX518/MAX519 Application Circuit slave addresses and therefore a maximum of four of
8 _______________________________________________________________________________________
SDA t t BUF SU, DAT tSU, STA tHD, STA t t LOW tHD, DAT SU, STO SCL tHIGH tHD, STA tR tF START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION Figure 2. Two-Wire Serial Interface Timing Diagram The address byte and pairs of command and output bytes are transmitted between the START and STOP con- ditions. The SDA state is allowed to change only while SCL is low, with the exception of START and STOP condi- µC REF0 +1V tions. SDA’s state is sampled, and therefore must remain REF1 +4V DUAL stable while SCL is high. Data is transmitted in 8-bit SDA SCL
MAX517/MAX518/MAX519
DAC bytes. Nine clock cycles are required to transfer the data R bits to the MAX517/MAX518/MAX519. Set SDA low dur- C MAX519 1kΩ SCL OUT0 OFFSET ADJUSTMENT ing the 9th clock cycle as the MAX517/MAX518/MAX519 SDA pull SDA low during this time. RC (see Figure 3) limits the AD0 OUT1 GAIN ADJUSTMENT current that flows during this time if SDA stays high for AD1 short periods of time. AD2 AD3
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmis- DUAL DAC sion with a START condition by transitioning SDA from high to low while SCL is high (Figure 5). When the mas- MAX518 ter has finished communicating with the slave, it issues SCL a STOP condition by transitioning SDA from low to high SDA OUT0 BRIGHTNESS ADJUSTMENT while SCL is high. The bus is then free for another AD0 OUT1 CONTRAST ADJUSTMENT transmission. AD1
The Slave Address
REF0 +2.5V The MAX517/MAX518/MAX519 each have a 7-bit long SINGLE slave address (Figure 6). The first three bits (MSBs) of DAC the slave address have been factory programmed and MAX517 SCL are always 010. In addition, the MAX517 and MAX518 OUT0 THRESHOLD ADJUSTMENT SDA have the next two bits factory programmed to 1s. The +5V AD0 logic state of the address inputs (AD0 and AD1 on the AD1 MAX517/MAX518; AD0, AD1, AD2, and AD3 on the MAX519) determine the LSB bits of the 7-bit slave address. These input pins may be connected to VDD or DGND, or they may be actively driven by TTL or CMOS logic levels. The MAX517/MAX518 have four possible Figure 3. MAX517/MAX518/MAX519 Application Circuit slave addresses and therefore a maximum of four of
8 _______________________________________________________________________________________