Datasheet STM32WB50CG (STMicroelectronics) - 10

Description STM32WB50CG 2 Description
The STM32WB50CG multiprotocol wireless and ultra-low-power device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low Energy SIG specification v5.0 or with IEEE 802.15.4-2011. They contain a dedicated Arm® Cortex® -M0+ for performing all the real-time low layer operation. The STM32WB50CG device is designed to be extremely low-power and are based on the high-performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. The Cortex®-M4 core features a Floating point unit (FPU) single precision that supports all Arm® single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security. Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors. The STM32WB50CG device embeds high-speed memories (Flash memory 1 Mbyte, up to 128 Kbyte of SRAM) and an extensive range of enhanced I/Os and peripherals. Direct data transfer between memory and peripherals and from memory to memory is supported by seven DMA channels with a full flexible channel mapping by the DMAMUX peripheral. The STM32WB50CG device embeds several mechanisms for embedded Flash memory and SRAM: readout protection, write protection and proprietary code readout protection. Portions of the memory can be secured for Cortex® -M0+ exclusive access. The AES encryption engine, PKA and RNG enable lower layer MAC and upper layer cryptography. A customer key storage feature may be used to keep the keys hidden. The device offers one fast 16-bit ADC. The STM32WB50CG device embeds a low-power RTC, one advanced 16-bit timer, one general-purpose 32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers. They also feature standard and advanced communication interfaces: • one USART (ISO 7816, IrDA, Modbus and Smartcard mode) • one I2C (SMBus/PMBus) • one SPI (up to 32 MHz) The STM32WB50CG operates in the -10 to +85 °C (+105 °C junction) temperature range from a 2 to 3.6 V power supply. A comprehensive set of power-saving modes enables the design of low-power applications. The STM32WB50CG includes independent power supplies for analog input for ADC. A VBAT dedicated supply allows the device to back up the LSE 32.768KHz oscillator, the RTC and the backup registers, thus enabling the STM32WB50CG to supply these functions even if the main VDD is not present through a CR2032-like battery, a Supercap or a small rechargeable battery. The STM32WB50CG is available in a 48-pin UFQFPN package. 10/120 DS13047 Rev 1 Document Outline 1 Introduction 2 Description Table 1. STM32WB50CG device features and peripheral counts Figure 1. STM32WB50CG block diagram 3 Functional overview 3.1 Architecture 3.2 Arm® Cortex®-M4 core with FPU 3.3 Memories 3.3.1 Adaptive real-time memory accelerator (ART Accelerator™) 3.3.2 Memory protection unit 3.3.3 Embedded Flash memory Table 2. Access status vs. readout protection level and execution modes 3.3.4 Embedded SRAM 3.4 Security and safety 3.5 Boot modes and FW update 3.6 RF subsystem 3.6.1 RF front-end block diagram Figure 2. STM32WB50CG RF front-end block diagram 3.6.2 BLE general description 3.6.3 802.15.4 general description 3.6.4 RF pin description Table 3. RF pin list 3.6.5 Typical RF application schematic Figure 3. STM32WB50CG external components for the RF part Table 4. Typical external components 3.7 Power supply management 3.7.1 Power supply schemes Figure 4. Power-up/down sequence Figure 5. Power supply overview 3.7.2 Linear voltage regulator 3.7.3 Power supply supervisor 3.7.4 Low-power modes Table 5. Features over all modes (continued) Table 6. STM32WB50CG modes overview (continued) 3.7.5 Reset mode 3.8 VBAT operation 3.9 Interconnect matrix Table 7. STM32WB50CG CPU1 peripherals interconnect matrix (continued) 3.10 Clocks and startup Figure 6. Clock tree 3.11 General-purpose inputs/outputs (GPIOs) 3.12 Direct memory access controller (DMA) Table 8. DMA implementation 3.13 Interrupts and events 3.13.1 Nested vectored interrupt controller (NVIC) 3.13.2 Extended Interrupts and Events Controller (EXTI) 3.14 Analog to digital converter (ADC) 3.14.1 Temperature sensor Table 9. Temperature sensor calibration values 3.14.2 Internal voltage reference (VREFINT) Table 10. Internal voltage reference calibration values 3.15 True random number generator (RNG) 3.16 Timers and watchdogs Table 11. Timer features 3.16.1 Advanced-control timer (TIM1) 3.16.2 General-purpose timers (TIM2, TIM16, TIM17) 3.16.3 Low-power timer (LPTIM1 and LPTIM2) 3.16.4 Independent watchdog (IWDG) 3.16.5 System window watchdog (WWDG) 3.16.6 SysTick timer 3.17 Real-time clock (RTC) and backup registers 3.18 Inter-integrated circuit interface (I2C) Table 12. I2C implementation 3.19 Universal synchronous/asynchronous receiver transmitter (USART) 3.20 Serial peripheral interface (SPI1) 3.21 Development support 3.21.1 Serial wire JTAG debug port (SWJ-DP) 4 Pinouts and pin description Figure 7. STM32WB50CG UFQFPN48 pinout(1)(2) Table 13. Legend/abbreviations used in the pinout table Table 14. STM32WB50CG pin and ball definitions (continued) Table 15. Alternate functions (continued) 5 Memory mapping 6 Electrical characteristics 6.1 Parameter conditions 6.1.1 Minimum and maximum values 6.1.2 Typical values 6.1.3 Typical curves 6.1.4 Loading capacitor 6.1.5 Pin input voltage Figure 8. Pin loading conditions Figure 9. Pin input voltage 6.1.6 Power supply scheme Figure 10. Power supply scheme 6.1.7 Current consumption measurement Figure 11. Current consumption measurement scheme 6.2 Absolute maximum ratings Table 16. Voltage characteristics Table 17. Current characteristics Table 18. Thermal characteristics 6.3 Operating conditions 6.3.1 Summary of main performance Table 19. Main performance at VDD = 3.3 V 6.3.2 General operating conditions Table 20. General operating conditions (continued) 6.3.3 RF BLE characteristics Table 21. RF transmitter BLE characteristics Table 22. RF transmitter BLE characteristics (1 Mbps) (continued) Table 23. RF receiver BLE characteristics (1 Mbps) (continued) Table 24. RF BLE power consumption for VDD = 3.3 V 6.3.4 RF 802.15.4 characteristics Table 25. RF transmitter 802.15.4 characteristics Table 26. RF receiver 802.15.4 characteristics Figure 12. Typical link quality indicator code vs. Rx level Figure 13. Typical energy detection (T = 27°C, VDD = 3.3 V) Table 27. RF 802.15.4 power consumption for VDD = 3.3 V 6.3.5 Operating conditions at power-up / power-down Table 28. Operating conditions at power-up / power-down 6.3.6 Embedded reset and power control block characteristics Table 29. Embedded reset and power control block characteristics (continued) 6.3.7 Embedded voltage reference Table 30. Embedded internal voltage reference Figure 14. VREFINT vs. temperature 6.3.8 Supply current characteristics Table 31. Current consumption in Run and Low-power run modes, code with data processing running from Flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V Table 32. Current consumption in Run and Low-power run modes, code with data processing running from SRAM1, VDD = 3.3 V Table 33. Typical current consumption in Run and Low-power run modes, with different codes running from Flash, ART enable (Cache ON Prefetch OFF), VDD= 3.3 V Table 34. Typical current consumption in Run and Low-power run modes, with different codes running from SRAM1, VDD = 3.3 V Table 35. Current consumption in Sleep and Low-power sleep modes, Flash memory ON Table 36. Current consumption in Low-power sleep modes, Flash memory in Power down Table 37. Current consumption in Stop 2 mode Table 38. Current consumption in Stop 1 mode Table 39. Current consumption in Stop 0 mode Table 40. Current consumption in Standby mode Table 41. Current consumption in Shutdown mode Table 42. Current consumption in VBAT mode Table 43. Current under Reset condition Table 44. Peripheral current consumption (continued) 6.3.9 Wakeup time from Low-power modes and voltage scaling transition times Table 45. Low-power mode wakeup timings (continued) Table 46. Regulator modes transition times 6.3.10 External clock source characteristics Table 47. HSE crystal requirements Table 48. HSE oscillator characteristics Table 49. Low-speed external user clock characteristics Figure 15. Typical application with a 32.768 kHz crystal 6.3.11 Internal clock source characteristics Table 50. HSI16 oscillator characteristics Figure 16. HSI16 frequency vs. temperature Table 51. MSI oscillator characteristics (continued) Figure 17. Typical current consumption vs. MSI frequency Table 52. HSI48 oscillator characteristics Figure 18. HSI48 frequency vs. temperature Table 53. LSI1 oscillator characteristics Table 54. LSI2 oscillator characteristics 6.3.12 PLL characteristics Table 55. PLL characteristics 6.3.13 Flash memory characteristics Table 56. Flash memory characteristics Table 57. Flash memory endurance and data retention 6.3.14 EMC characteristics Table 58. EMS characteristics Table 59. EMI characteristics 6.3.15 Electrical sensitivity characteristics Table 60. ESD absolute maximum ratings Table 61. Electrical sensitivities 6.3.16 I/O current injection characteristics Table 62. I/O current injection susceptibility 6.3.17 I/O port characteristics Table 63. I/O static characteristics Figure 19. I/O input characteristics Table 64. Output voltage characteristics Table 65. I/O AC characteristics (continued) 6.3.18 NRST pin characteristics Table 66. NRST pin characteristics Figure 20. Recommended NRST pin protection 6.3.19 Analog switches booster Table 67. Analog switches booster characteristics 6.3.20 Analog-to-Digital converter characteristics Table 68. ADC characteristics (continued) Table 69. ADC sampling time (continued) Table 70. ADC accuracy - Limited test conditions 1 Table 71. ADC accuracy - Limited test conditions 2 Table 72. ADC accuracy - Limited test conditions 3 Figure 21. ADC accuracy characteristics Figure 22. Typical connection diagram using the ADC 6.3.21 Temperature sensor characteristics Table 73. TS characteristics 6.3.22 VBAT monitoring characteristics Table 74. VBAT monitoring characteristics Table 75. VBAT charging characteristics 6.3.23 Timer characteristics Table 76. TIMx characteristics Table 77. IWDG min/max timeout period at 32 kHz (LSI1) 6.3.24 Communication interfaces characteristics Table 78. Minimum I2CCLK frequency in all I2C modes Table 79. I2C analog filter characteristics Table 80. SPI characteristics Figure 23. SPI timing diagram - slave mode and CPHA = 0 Figure 24. SPI timing diagram - slave mode and CPHA = 1 Figure 25. SPI timing diagram - master mode 7 Package information 7.1 UFQFPN48 package information Figure 26. UFQFPN - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline Table 81. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data Figure 27. UFQFPN48 - 48 leads, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint Figure 28. UFQFPN48 marking example (package top view) 7.2 Thermal characteristics Table 82. Package thermal characteristics 7.2.1 Reference document 7.2.2 Selecting the product temperature range 8 Ordering information 9 Revision history Table 83. Document revision history