Datasheet ARG81800 (Allegro) - 8
Hersteller | Allegro |
Beschreibung | 40 V, 500 mA / 1.0 A Synchronous Buck Regulators with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD |
Seiten / Seite | 42 / 8 — 40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow … |
Dateiformat / Größe | PDF / 4.0 Mb |
Dokumentensprache | Englisch |
40 V, 500 mA / 1.0 A Synchronous Buck Regulators. ARG81800. with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD
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40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, –40°C ≤ TJ ≤ 150°C, unless otherwise specified Characteristics Symbol Test Conditions Min. Typ. Max. Unit ERROR AMPLIFIER
Feedback Input Bias Current [2] IFB VFB = 800 mV –40 – –15 nA Open-Loop Voltage Gain AVOL − 65 − dB V Transconductance gm FB > 400 mV 550 750 950 μA/V 0 V < VFB < 400 mV 275 375 550 μA/V Output Current IEA − ±75 − μA COMP Pull-Down Resistance RCOMP FAULT = 1 or HICCUP = 1 − 1 − kΩ
SOFT START
Startup (Source) Current ISS HICCUP = FAULT = 0 −30 −20 −10 µA Hiccup/Dropout (Sink) Current IHIC HICCUP = 1 or Dropout Mode 1 2.2 5 µA Soft Start Delay Time [3] tdSS CSS = 22 nF − 440 − µs Soft Start Ramp Time [3] tSS CSS = 22 nF − 880 − µs FAULT/HICCUP Reset Voltage VSSRST VSS falling due to HICCUP or FAULT − 200 275 mV Hiccup OCP (and LP) Counter Enable Threshold VHIC/LP(EN) VSS rising − 2.3 − V 0 V < VFB < 200 mV – fSW / 4 – – Soft Start Frequency Foldback fSW(SS) 200 mV < VFB < 400 mV – fSW / 2 – – 400 mV < VFB – fSW – – Maximum Voltage VSS(MAX) VEN = 0 V or FAULT without HICCUP − VVREG − − Pull-Down Resistance RSS(FLT) 2 kΩ
HICCUP MODE COUNTS
High-Side Overcurrent Count HICOC After VSS > VHIC/LP(EN) − 120 − fSW counts SW Short-to-Ground Count HICSW(GND) − 2 − fSW counts BOOT Short Circuit Count HICBOOT(SC) − 120 − fSW counts BOOT Open Circuit Count [3] HICBOOT(OC) − 7 − fSW counts Continued on next page... 8 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing