Datasheet ARG81800 (Allegro) - 5

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40 V, 500 mA / 1.0 A Synchronous Buck Regulators ARG81800 with Ultralow Quiescent Current, SYNCIN, CLKOUT, and PGOOD PINOUT DIAGRAM AND TERMINAL LIST Terminal List Table
VIN VIN NC PGND PGND
Number Name Function
20 19 18 17 16 This pin supplies the drive for the high-side N-channel MOSFET. Connect a 100 nF BOOT 1 15 VREG 1 BOOT ceramic capacitor from BOOT to SW. Do not add any external resistor in series with the boot capacitor. SW 2 14 FB 2, 3 SW Regulator switch node output pins. Connect these pins to power inductor with a short SW 3 PAD 13 BIAS and wide PCB trace. SS 4 12 PGOOD 4 SS Soft start pin. Connect a capacitor, CSS, from this pin to GND to set the start-up time. This capacitor also determines the hiccup period during overcurrent. EN 5 11 COMP This pin must be set high to enable the ARG81800. If this pin is low, the ARG81800 will enter a very low current shutdown or “SLEEP” state where VOUT = 0 V. If the application 6 7 8 9 10 5 EN does not require a logic level controlled enable, then this pin can be tied directly to VIN. IN Also, if this pin is floated, it will be pulled low by an internal pull-down resistor, disabling OUT the ARG81800. GND FSET CLK SYNC Dual function pin: Clock output pin for “Master” operation. Frequency dithering is added PWM/AUTO to this pin when the ARG81800 is operating as a Master. For “Follower” operation, this 6 CLKOUT pin must be connected to VREG so dithering will not be internally added to SYNCIN; see Figure 1. The exact functionality of this pin is dependent on the status of the SYNCIN pin; see Table 1 and the description for SYNCIN for additional details.
Package ES, 20-Pin QFN
Triple function pin: High/Low/ExtClock. Setting this pin high sets CLKOUT to the internal
Pinout Diagram
oscillator frequency (fSW) but with 180 degree phase shift. Setting this pin low disables 7 SYNCIN the CLKOUT pin. Applying an external clock (at fSYNC) forces PWM mode, synchronizes the PWM switching frequency to the external clock plus dithering, and sets CLKOUT to the same dithered frequency but with 180 degree phase shift. See Table 1 for details. 8 GND Analog ground pin. 9 FSET Frequency setting pin. A resistor, RFSET, from this pin to GND sets the oscillator frequency, fSW. 10 PWM/ Mode selection pin. High/Low. Setting this pin high forces PWM mode. Setting this pin AUTO low allows AUTO changeover between PWM and LP mode based on the load current. 11 COMP Output of the error amplifier and compensation node for the current mode control loop. Connect a series RC network from this pin to GND for loop compensation. Power good output signal. PGOOD is an open-drain output that remains low until 12 PGOOD the output has achieved regulation for tdPG(SU). The PGOOD pull-up resistor can be connected to VREG, VOUT, or any external supply voltage less than 5.5 V. PGOOD will pull low if the output voltage (VOUT) is out of range. 13 BIAS Connect this pin to the output of the regulator. This pin supplies the internal circuitry when the voltage level is high enough. 14 FB Feedback (negative) input to the error amplifier. Connect a resistor divider from the regulators output, VOUT, to this pin to program the output voltage. 15 VREG Internal voltage regulator bypass capacitor pin. Connect a 4.7 µF capacitor from this pin to PGND and place it very close to the ARG81800. 16, 17 PGND Power ground pins for the lower MOSFET, gate driver, and BOOT charge circuit. 18 NC No connection. Power input for the control circuits and the drain of the internal high-side N-channel 19, 20 VIN MOSFET. Bypass VIN to PGND with an X7R or X8R ceramic capacitor. Place the capacitor as close to the VIN and PGND pins as possible. Additional capacitors may be required depending on the application to comply with EMC requirements. ‒ PAD Exposed pad of the package providing enhanced thermal dissipation. This pad must be connected to the ground plane of the PCB with at least 6 vias directly in the pad. 5 Allegro MicroSystems 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Diagram Selection Guide Absolute Maximum Ratings Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Electrical Characteristics Typical Performance Characteristics Functional Description Overview Reference Voltage Internal VREG Regulator Oscillator/Switching Frequency Synchronization (SYNCIN) and Clock Output (CLOCKOUT) Frequency Dither Transconductance Error Amplifier Compensation Components Power MOSFETs BOOT Regulator Soft Start (Startup) and Inrush Current Control Slope Compensation Pre-Biased Startup Dropout PGOOD Output Current Sense Amplifier Pulse-Width Modulation (PWM) Low-Power (LP) Mode Protection Features Undervoltage Lockout (UVLO) Pulse-by-Pulse Peak Current Protection (PCP) Overcurrent Protection (OCP) and Hiccup Mode BOOT Capacitor Protection Asynchronous Diode Protection Overvoltage Protection (OVP) SW Pin Protection Pin-to-Ground and Pin-to-Short Protections Thermal Shutdown (TSD) Application Information Design and Component Selection PWM Switching Frequency (RFSET) Output Voltage Setting Output Inductor (LO) Output Capacitors (CO) Output Voltage Ripple – Ultralow-IQ LP Mode Input Capacitors Bootstrap Capacitor Soft Start and Hiccup Mode Timing (CSS) Compensation Components (RZ, CZ, and CP) Power Stage Error Amplifier A Generalized Tuning Procedure Power Dissipation and Thermal Calculations EMI/EMC Aware PCB Design Typical Reference Designs Package Outline Drawing