Datasheet GW1NRF (GOWIN Semiconductor) - 8

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List of Tables
Table 1-1 Abbreviations and Terminologies ... 2 Table 2-1 Product Resources ... 7 Table 2-2 Package Information, Max. I/O and LVDS Pairs .. 8 Table 3-1 Register Description in CLS ... 19 Table 3-2 Output I/O Standards and Configuration Options .. 21 Table 3-3 Output I/O Standards and Configuration Options .. 22 Table 3-4 B-SRAM Signals .. 31 Table 3-5 Memory Size Configuration .. 32 Table 3-6 Dual Port Mixed Read/Write Data Width Configuration ... 32 Table 3-7 Semi Dual Port Mixed Read/Write Data Width Configuration .. 32 Table 3-8 Single Port Block Memory Configuration ... 34 Table 3-9 Dual Port Memory Configuration .. 35 Table 3-10Semi Dual Port Memory Configuration ... 36 Table 3-11 Block ROM Configuration ... 36 Table 3-12 Clock Operations in Different B-SRAM Modes .. 38 Table 3-13 Flash Module Signal Description ... 41 Table 3-14 Truth Table in User Mode ... 42 Table 3-15 DSP Ports Description ... 43 Table 3-16 Internal Registers Description .. 44 Table 3-17 PLL Ports Definition.. 50 Table 3-18 GW1NRF-4B Oscillator Output Frequency Options .. 53 Table 4-1 Absolute Max. Ratings ... 54 Table 4-2 Recommended Operating Conditions .. 54 Table 4-3 Power Supply Ramp Rates .. 55 Table 4-4 Hot Socket Specifications .. 55 Table 4-5 GW1NRF ESD – HBM ... 55 Table 4-6 GW1NRF ESD - CDM .. 55 Table 4-7 DC Electrical Characteristics under Recommended Operating Conditions ... 55 Table 4-8 Static Supply Current1 .. 57 Table 4-9 DC Characteristics, DCDC Step-Down Configuration, VBAT2=3.0V .. 57 Table 4-10 DC Characteristics, DCDC Step-Up Configuration, VBAT2=1.5V ... 58 Table 4-11 Low Frequency Crystal Oscillator Specifications ... 59 DS891-1.0E v Document Outline Disclaimer Revision History Contents List of Figures List of Tables 1 About This Guide 1.1 Purpose 1.2 Supported Products 1.3 Related Documents 1.4 Abbreviations and Terminology 1.5 Support and Feedback 2 General Description 2.1 Features 2.2 Product Resources 2.3 Package Information 3 Architecture 3.1 Architecture Overview 3.2 SoC System FPU Memories Security Peripherals 3.2.1 Bluetooth Module Bluetooth Controller Mode Bluetooth Companion Mode Bluetooth Application Mode 3.2.2 Timers 3.2.3 Power Management DC DC Switching Power Supply Supply Monitoring 3.2.4 RF Description 3.2.5 Operating Modes 3.2.6 Software Development 3.3 Configurable Function Unit 3.3.1 CLU Register 3.3.2 CRU 3.4 IOB 3.4.1 I/O Buffer 3.4.2 True LVDS Design 3.4.3 I/O Logic IODELAY I/O Register IEM De-serializer DES and Clock Domain Transfer Serializer SER 3.4.4 I/O Logic Modes Basic Mode SDR Mode Generic DDR Mode IDES4 OSER4 Mode IVideo Mode OVideo Mode IDES8 Mode OSER8 Mode IDES10 Mode OSER10 Mode 3.5 Block SRAM (B-SRAM) 3.5.1 Introduction 3.5.2 Configuration Mode 3.5.3 Mixed Data Bus Width Configuration 3.5.4 Byte-enable 3.5.5 Parity Bit 3.5.6 Synchronous operation 3.5.7 Power up Conditions 3.5.8 Operation Modes Single Port Mode Dual Port Mode Semi-Dual Port Mode Read Only 3.5.9 B-SRAM Operation Modes Read Mode Pipeline Mode Bypass Mode Write Mode 3.5.10 Clock Operations Independent Clock Mode Read/Write Clock Operation Single Port Clock Mode 3.6 User Flash 3.6.1 Introduction 3.6.2 User Flash Ports 3.6.3 User Flash Mode Truth Table User Modes 3.7 DSP 3.7.1 Introduction Macro PADD MULT ALU 3.7.2 DSP Operations 3.8 Clock 3.8.1 Global Clock 3.8.2 PLL 3.8.3 HCLK 3.8.4 DLL 3.9 Long Wire (LW) 3.10 Global Set/Reset (GSR) 3.11 Programming Configuration 3.11.1 SRAM Configuration 3.11.2 Flash Configuration 3.12 On Chip Oscillator 4 AC/DC Characteristics 4.1 Operating Conditions 4.2 ESD 4.3 DC Characteristics 4.3.1 Static Current 4.3.2 RF Parameters 4.3.3 I/O Characteristics 4.4 Switching Characteristics 4.4.1 Internal Switching Characteristics 4.4.2 External Switching Characteristics 4.5 User Flash Characteristics 4.5.1 DC Characteristics1 4.5.2 Timing Parameters1,5,6 4.5.3 Operation Timing Diagrams 4.6 Configuration Interface Timing Specification 4.6.1 JTAG Port Timing Specifications 4.6.2 AUTO BOOT Port Timing Specifications 4.6.3 SSPI Port Timing Specifications 4.6.4 MSPI Port Timing Specifications 4.6.5 DUAL BOOT 4.6.6 CPU 4.6.7 SERIAL 5 Ordering Information 5.1 Part Name 5.2 Package Mark