Datasheet PIC18(L)F2X/4X/5XK42 (Microchip) - 10
| Hersteller | Microchip |
| Beschreibung | Highly Integrated 8-Bit PIC Microcontrollers in 28-to 48-Pins |
| Seiten / Seite | 18 / 10 — PIC18(L)F2X/4X/5XK4. TABLE 3:. 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42) … |
| Dateiformat / Größe | PDF / 208 Kb |
| Dokumentensprache | Englisch |
PIC18(L)F2X/4X/5XK4. TABLE 3:. 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42) (CONTINUED). ) R. /SSO. n-C. I/O. 2 I. asic. SPI. e R. ros. DSM. NCO. t-o
Modelllinie für dieses Datenblatt
- PIC18F27K42-E/ML PIC18F27K42-E/MLVAO PIC18F27K42-E/MX PIC18F27K42-E/SO PIC18F27K42-E/SP PIC18F27K42-E/SS PIC18F27K42-I/ML PIC18F27K42-I/MX PIC18F27K42-I/SO PIC18F27K42-I/SP PIC18F27K42-I/SS PIC18F27K42T-E/ML PIC18F27K42T-E/MLVAO PIC18F27K42T-I/ML PIC18F27K42T-I/MX PIC18F27K42T-I/SO PIC18F27K42T-I/SS PIC18LF27K42-E/ML PIC18LF27K42-E/MX PIC18LF27K42-E/SO PIC18LF27K42-E/SP PIC18LF27K42-E/SS PIC18LF27K42-I/ML PIC18LF27K42-I/MX PIC18LF27K42-I/SO PIC18LF27K42-I/SP PIC18LF27K42-I/SS PIC18LF27K42T-E/ML PIC18LF27K42T-I/ML PIC18LF27K42T-I/MX PIC18LF27K42T-I/SO PIC18LF27K42T-I/SS
- PIC18F45K42-E/ML PIC18F45K42-E/MV PIC18F45K42-E/P PIC18F45K42-E/PT PIC18F45K42-I/ML PIC18F45K42-I/MV PIC18F45K42-I/P PIC18F45K42-I/PT PIC18F45K42T-I/ML PIC18F45K42T-I/MV PIC18F45K42T-I/MVVAO PIC18F45K42T-I/PT PIC18LF45K42-E/ML PIC18LF45K42-E/MV PIC18LF45K42-E/P PIC18LF45K42-E/PT PIC18LF45K42-I/ML PIC18LF45K42-I/MV PIC18LF45K42-I/P PIC18LF45K42-I/PT PIC18LF45K42T-I/ML PIC18LF45K42T-I/MV PIC18LF45K42T-I/PT
- PIC18F46K42-E/ML PIC18F46K42-E/MV PIC18F46K42-E/MVVAO PIC18F46K42-E/P PIC18F46K42-E/PT PIC18F46K42-I/ML PIC18F46K42-I/MV PIC18F46K42-I/P PIC18F46K42-I/PT PIC18F46K42T-I/ML PIC18F46K42T-I/MV PIC18F46K42T-I/PT PIC18LF46K42-E/ML PIC18LF46K42-E/MV PIC18LF46K42-E/P PIC18LF46K42-E/PT PIC18LF46K42-I/ML PIC18LF46K42-I/MV PIC18LF46K42-I/P PIC18LF46K42-I/PT PIC18LF46K42T-I/ML PIC18LF46K42T-I/MV PIC18LF46K42T-I/PT
- PIC18F47K42-E/ML PIC18F47K42-E/MV PIC18F47K42-E/P PIC18F47K42-E/PT PIC18F47K42-I/ML PIC18F47K42-I/MV PIC18F47K42-I/P PIC18F47K42-I/PT PIC18F47K42T-I/ML PIC18F47K42T-I/MV PIC18F47K42T-I/PT PIC18LF47K42-E/ML PIC18LF47K42-E/MV PIC18LF47K42-E/P PIC18LF47K42-E/PT PIC18LF47K42-I/ML PIC18LF47K42-I/MV PIC18LF47K42-I/P PIC18LF47K42-I/PT PIC18LF47K42T-I/ML PIC18LF47K42T-I/MV PIC18LF47K42T-I/PT
- PIC18F55K42-E/MV PIC18F55K42-E/PT PIC18F55K42-I/MV PIC18F55K42-I/PT PIC18F55K42T-E/MV PIC18F55K42T-I/MV PIC18F55K42T-I/PT PIC18LF55K42-E/MV PIC18LF55K42-E/PT PIC18LF55K42-I/MV PIC18LF55K42-I/PT PIC18LF55K42-I/PTC01 PIC18LF55K42T-I/MV PIC18LF55K42T-I/PT PIC18LF55K42T-I/PTC01
Textversion des Dokuments
DS4
PIC18(L)F2X/4X/5XK4 TABLE 3: 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42) (CONTINUED)
0001861B-p
P ) R e t ge /SSO c c LK N n n te M a
age 10
IC F rs e (C h O re e )Q MT fe to D PW /S C e C ra s C RT /S G C nc n-C I/O IP (U a 2 I rs nd re asic in AD SPI e R DA p ros DSM CW CL NCO t-o m UA fe B -P C me P a e up SPD Ti C 28 ltag Co ro R rr in o C k V Ze te -P In 8 loc 2 C
RC0 11 8 ANC0 — — — — — — — — T1CKI
(1)
— — — — — IOCC0 SOSCO T3CKI
(1)
T3G
(1)
SMTWIN1
(1)
RC1 12 9 ANC1 — — — — — — — — SMTSIG1
(1)
CCP2
(1)
— — — — IOCC1 SOSCI
A d
RC2 13 10 ANC2 — — — — — — — — T5CKI
(1)
CCP1
(1)
— — — — IOCC2 —
va
RC3 14 11 ANC3 — — — — SCL1
(3,4)
SCK1
(1)
— — T2IN
(1)
— — — — — IOCC3 —
nce Inf
RC4 15 12 ANC4 — — — — SDA1
(3,4)
SDI1
(1)
— — — — — — — — IOCC4 — RC5 16 13 ANC5 — — — — — — — — T4IN
(1)
— — — — — IOCC5 — RC6 17 14 ANC6 — — — — — — CTS1
(1)
— — — — — — — IOCC6 —
2
RC7 18 15 ANC7 — — — — — — RX1
(1)
— — — — — — — IOCC7 —
o r
RE3 1 26 — — — — — — — — — — — — — — — IOCE3 MCLR
m
VPP
at
VDD 20 17 — — — — — — — — — — — — — — — — —
ion
VSS 8, 5, — — — — — — — — — — — — — — — — — 19 16 OUT
(2)
— — ADGRDA — — C1OUT — SDA1 SS1 RTS1 DSM TMR0 CCP1 CWG1A CLC1OUT NCO CLKR — — ADGRDB C2OUT SCL1 SCK1 TXDE1 CCP2 CWG1B CLC2OUT SDA2 SDO1 TX1 CCP3 CWG1C CLC3OUT SCL2 RTS2 CCP4 CWG1D CLC4OUT TXDE2 PWM5OUT CWG2A TX2 PWM6OUT CWG2B PWM7OUT CWG2C PWM8OUT CWG2D 20 CWG3A 16 M CWG3B CWG3C CWG3D icrochip
Note 1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2:
All output signals shown in this row are PPS remappable.
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. T
4:
These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels e c will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. hnology Inc. Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Digital Peripherals (Continued) Analog Peripherals Flexible Oscillator Structure TABLE 1: PIC18(L)F2X/4X/5XK42 Family Types TABLE 2: Packages FIGURE 1: 28-Pin SPDIP, SOIC, SSOP for PIC18(L)F2XK42 FIGURE 2: 28-Pin UQFN (4x4) for PIC18(L)F2XK42 FIGURE 3: 28-Pin QFN (6x6x0.9 mm) for PIC18(L)F2XK42 FIGURE 4: 40-Pin PDIP for PIC18(L)F4XK42 FIGURE 5: 40-Pin UQFN (5x5x0.5 mm) for PIC18(L)F4XK42 FIGURE 6: 44-Pin QFN (8x8x0.9 mm) for PIC18(L)F5XK42 FIGURE 7: 44-Pin TQFP For PIC18(L)F4XK42 FIGURE 8: 48-Pin TQFP/UQFN for PIC18(L)F5XK42 TABLE 3: 28-Pin Allocation Table (PIC18(L)F2XK42) TABLE 4: 40/44-Pin Allocation Table For PIC18(L)F4XK42, PIC18(L)F5XK42 TABLE 5: 48-Pin Allocation Table for PIC18(L)F5XK42 Trademarks Worldwide Sales
PIC18(L)F2X/4X/5XK4 TABLE 3: 28-PIN ALLOCATION TABLE (PIC18(L)F2XK42) (CONTINUED)
0001861B-p
P ) R e t ge /SSO c c LK N n n te M a
age 10
IC F rs e (C h O re e )Q MT fe to D PW /S C e C ra s C RT /S G C nc n-C I/O IP (U a 2 I rs nd re asic in AD SPI e R DA p ros DSM CW CL NCO t-o m UA fe B -P C me P a e up SPD Ti C 28 ltag Co ro R rr in o C k V Ze te -P In 8 loc 2 C
RC0 11 8 ANC0 — — — — — — — — T1CKI
(1)
— — — — — IOCC0 SOSCO T3CKI
(1)
T3G
(1)
SMTWIN1
(1)
RC1 12 9 ANC1 — — — — — — — — SMTSIG1
(1)
CCP2
(1)
— — — — IOCC1 SOSCI
A d
RC2 13 10 ANC2 — — — — — — — — T5CKI
(1)
CCP1
(1)
— — — — IOCC2 —
va
RC3 14 11 ANC3 — — — — SCL1
(3,4)
SCK1
(1)
— — T2IN
(1)
— — — — — IOCC3 —
nce Inf
RC4 15 12 ANC4 — — — — SDA1
(3,4)
SDI1
(1)
— — — — — — — — IOCC4 — RC5 16 13 ANC5 — — — — — — — — T4IN
(1)
— — — — — IOCC5 — RC6 17 14 ANC6 — — — — — — CTS1
(1)
— — — — — — — IOCC6 —
2
RC7 18 15 ANC7 — — — — — — RX1
(1)
— — — — — — — IOCC7 —
o r
RE3 1 26 — — — — — — — — — — — — — — — IOCE3 MCLR
m
VPP
at
VDD 20 17 — — — — — — — — — — — — — — — — —
ion
VSS 8, 5, — — — — — — — — — — — — — — — — — 19 16 OUT
(2)
— — ADGRDA — — C1OUT — SDA1 SS1 RTS1 DSM TMR0 CCP1 CWG1A CLC1OUT NCO CLKR — — ADGRDB C2OUT SCL1 SCK1 TXDE1 CCP2 CWG1B CLC2OUT SDA2 SDO1 TX1 CCP3 CWG1C CLC3OUT SCL2 RTS2 CCP4 CWG1D CLC4OUT TXDE2 PWM5OUT CWG2A TX2 PWM6OUT CWG2B PWM7OUT CWG2C PWM8OUT CWG2D 20 CWG3A 16 M CWG3B CWG3C CWG3D icrochip
Note 1:
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins.
2:
All output signals shown in this row are PPS remappable.
3:
This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. T
4:
These pins are configured for I2C and SMBus 3.0/2.0 logic levels; The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS assignments to the other pins (e.g., RA5) will operate, but input logic levels e c will be standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBUS input buffer thresholds. hnology Inc. Document Outline Description Core Features Memory Operating Characteristics Power-Saving Functionality eXtreme Low-Power (XLP) Features Digital Peripherals Digital Peripherals (Continued) Analog Peripherals Flexible Oscillator Structure TABLE 1: PIC18(L)F2X/4X/5XK42 Family Types TABLE 2: Packages FIGURE 1: 28-Pin SPDIP, SOIC, SSOP for PIC18(L)F2XK42 FIGURE 2: 28-Pin UQFN (4x4) for PIC18(L)F2XK42 FIGURE 3: 28-Pin QFN (6x6x0.9 mm) for PIC18(L)F2XK42 FIGURE 4: 40-Pin PDIP for PIC18(L)F4XK42 FIGURE 5: 40-Pin UQFN (5x5x0.5 mm) for PIC18(L)F4XK42 FIGURE 6: 44-Pin QFN (8x8x0.9 mm) for PIC18(L)F5XK42 FIGURE 7: 44-Pin TQFP For PIC18(L)F4XK42 FIGURE 8: 48-Pin TQFP/UQFN for PIC18(L)F5XK42 TABLE 3: 28-Pin Allocation Table (PIC18(L)F2XK42) TABLE 4: 40/44-Pin Allocation Table For PIC18(L)F4XK42, PIC18(L)F5XK42 TABLE 5: 48-Pin Allocation Table for PIC18(L)F5XK42 Trademarks Worldwide Sales