Datasheet MCP616, MCP617, MCP618, MCP619 (Microchip) - 3

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MCP616/7/8/9 1.0 ELECTRICAL † Notice:
Stresses above those listed under “Absolute
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those
Absolute Maximum Ratings †
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended VDD – VSS ..7.0V periods may affect device reliability. Current at Analog Input Pins (VIN+ and VIN–)..±2 mA
††
See
Section 4.1.2 “Input Voltage and Current Limits”
. Analog Inputs (VIN+ and VIN–) †† .. VSS – 0.3V to VDD + 0.3V All other Inputs and Outputs .. VSS – 0.3V to VDD + 0.3V Difference Input Voltage .. |VDD – VSS| Output Short Circuit Current .. Continuous Current at Output and Supply Pins ..±30 mA Storage Temperature ... –65°C to +150°C Maximum Junction Temperature (TJ)... .+150°C ESD Protection On All Pins (HBM; MM)   4 kV; 400V
DC ELECTRICAL CHARACTERISTICS Electrical Specifications:
Unless otherwise indicated, VDD = +2.3V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT  VDD/2 and RL = 100 kto VDD/2.
Parameters Sym Min Typ Max Units Conditions Input Offset
Input Offset Voltage V -150 — +150 µV OS Input Offset Drift with Temperature V /T OS A — ±2.5 — µV/°C TA = -40°C to +85°C Power Supply Rejection PSRR 86 105 — dB
Input Bias Current and Impedance
Input Bias Current IB -35 -15 -5 nA At Temperature IB -70 -21 — nA TA = -40°C At Temperature IB — -12 — nA TA = +85°C Input Offset Current IOS — ±0.15 — nA Common-mode Input Impedance ZCM — 600||4 — M||pF Differential Input Impedance ZDIFF — 3||2 — M||pF
Common-mode
Common-mode Input Voltage Range VCMR VSS VDD – 0.9 V Common-mode Rejection Ratio CMRR 80 100 — dB VDD = 5.0V, VCM = 0.0V to 4.1V
Open-Loop Gain
DC Open-Loop Gain (large signal) AOL 100 120 — dB RL = 25 kto VDD/2, VOUT = 0.05V to VDD – 0.05V DC Open-Loop Gain (large signal) AOL 95 115 — dB RL = 5 k to VDD/2, VOUT = 0.1V to VDD – 0.1V
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD - 20 mV RL = 25 k to VDD/2, 0.5V input overdrive VOL, VOH VSS + 45 — VDD - 60 mV RL = 5 k to VDD/2, 0.5V input overdrive Linear Output Voltage Range VOUT VSS + 50 — VDD - 50 mV RL = 25 k to VDD/2, AOL  100 dB VOUT VSS + 100 — VDD - 100 mV RL = 5 k to VDD/2, AOL 95 dB Output Short Circuit Current ISC — ±7 — mA VDD = 2.3V ISC — ±17 — mA VDD = 5.5V
Power Supply
Supply Voltage VDD 2.3 — 5.5 V Quiescent Current per Amplifier IQ 12 19 25 µA IO = 0  2019 Microchip Technology Inc. DS20001613D-page 3 Document Outline 2.3V to 5.5V Micropower Bi-CMOS Op Amps Features Typical Applications Design Aids Input Offset Voltage Description Package Types 1.0 Electrical Characteristics Absolute Maximum Ratings † DC Electrical Characteristics AC Electrical Characteristics MCP618 Chip Select (CS) Electrical Characteristics FIGURE 1-1: Timing Diagram for the CS Pin on the MCP618. Temperature Characteristics 1.1 Test Circuits FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage at VDD = 5.5V. FIGURE 2-2: Input Offset Voltage at VDD = 2.3V. FIGURE 2-3: Input Bias Current at VDD = 5.5V. FIGURE 2-4: Input Offset Voltage Drift at VDD = 5.5V. FIGURE 2-5: Input Offset Voltage Drift at VDD = 2.3V. FIGURE 2-6: Input Offset Current at VDD = 5.5V. FIGURE 2-7: Input Offset Voltage vs. Ambient Temperature. FIGURE 2-8: Quiescent Current vs. Ambient Temperature. FIGURE 2-9: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 5 kW. FIGURE 2-10: Input Bias, Offset Currents vs. Ambient Temperature. FIGURE 2-11: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-12: Maximum Output Voltage Swing vs. Ambient Temperature at RL = 25 kW. FIGURE 2-13: Output Short Circuit Current vs. Ambient Temperature. FIGURE 2-14: Slew Rate vs. Ambient Temperature. FIGURE 2-15: Input Bias, Offset Currents vs. Common-mode Input Voltage. FIGURE 2-16: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. FIGURE 2-17: Input Offset Voltage vs. Common-mode Input Voltage. FIGURE 2-18: Input Offset Voltage vs. Output Voltage. FIGURE 2-19: Quiescent Current vs. Power Supply Voltage. FIGURE 2-20: DC Open-Loop Gain vs. Load Resistance. FIGURE 2-21: Gain-Bandwidth Product, Phase Margin vs. Load Resistance. FIGURE 2-22: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-23: DC Open-Loop Gain vs. Power Supply Voltage. FIGURE 2-24: Channel-to-Channel Separation vs. Frequency (MCP617 and MCP619 only). FIGURE 2-25: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-26: Input Noise Voltage, Current Densities vs. Frequency. FIGURE 2-27: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-28: CMRR, PSRR vs. Frequency. FIGURE 2-29: Maximum Output Voltage Swing vs. Frequency. FIGURE 2-30: Small-Signal, Inverting Pulse Response. FIGURE 2-31: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-32: Chip Select (CS) to Amplifier Output Response Time (MCP618 only). FIGURE 2-33: The MCP616/7/8/9 Show No Phase Reversal. FIGURE 2-34: Large-Signal, Inverting Pulse Response. FIGURE 2-35: Chip Select (CS) Internal Hysteresis (MCP618 only). FIGURE 2-36: Measured Input Current vs. Input Voltage (below VSS). 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Chip Select Digital Input (CS) 3.4 Power Supply Pins (VDD, VSS) 4.0 Applications Information 4.1 Rail-to-Rail Inputs Phase Reversal Input Voltage and Current Limits FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. Normal Operation 4.2 DC Offsets FIGURE 4-3: Example Circuit for Calculating DC Offset. FIGURE 4-4: Equivalent DC Circuit. EQUATION 4-1: 4.3 Rail-to-Rail Output 4.4 Capacitive Loads FIGURE 4-5: Output Resistor, RISO stabilizes large capacitive loads. FIGURE 4-6: Recommended RISO Values for Capacitive Loads. 4.5 MCP618 Chip Select (CS) 4.6 Supply Bypass 4.7 Unused Op Amps FIGURE 4-7: Unused Op Amps. 4.8 PCB Surface Leakage FIGURE 4-8: Example Guard Ring Layout for Inverting Gain. 4.9 Application Circuits FIGURE 4-9: High Gain Pre-amplifier. FIGURE 4-10: Two-Op Amp Instrumentation Amplifier. FIGURE 4-11: Three-Op Amp Instrumentation Amplifier. FIGURE 4-12: Precision Gain with Good Load Isolation. 5.0 Design Aids 5.1 SPICE Macro Model 5.2 Mindi™ Circuit Designer & Simulator 5.3 Microchip Advanced Part Selector (MAPS) 5.4 Analog Demonstration and Evaluation Boards 5.5 Application Notes 6.0 Packaging Information 6.1 Package Marking Information Appendix A: Revision History Product Identification System Worldwide Sales and Service