Datasheet PIC16(L)F18325/18345 (Microchip) - 8

DS40001795H-page
PIC16(L)F18325/18345 TABLE 2: 20-PIN ALLOCATION TABLE (PIC16(L)F18345) (CONTINUED) (2) I/O ADC NCO DAC DSM imers CCP CLC T PWM CWG MSSP CLKR Reference EUSART Interrupt Pull-up Basic
8
20-Pin UQFN Comparator 20-Pin PDIP/SOIC/SSOP
RC3 7 4 ANC3 — C1IN3- — — MDMIN
(1)
— CCP2
(1)
— — — — CLCIN1
(1)
— IOC Y — C2IN3- RC4 6 3 ANC4 — — — — — — — — — — — — — IOC Y — RC5 5 2 ANC5 — — — — MDCIN2
(1)
— CCP1
(1)
— — — — — — IOC Y — RC6 8 5 ANC6 — — — — — — — — — SS1
(1)
— — — IOC Y — RC7 9 6 ANC7 — — — — — — — — — — — — — IOC Y — VDD 1 18 — — — — — — — — — — — — — — — — VDD VSS 20 17 — — — — — — — — — — — — — — — — VSS — — — — C1OUT NCO1 — DSM TMR0 CCP1 PWM5 CWG1A SDO1 DT CLC1OUT CLKR — — — CWG2A SDO2 — — — — C2OUT — — — — CCP2 PWM6 CWG1B SCK1 CK CLC2OUT — — — — CWG2B SCK2 OUT
(2)
— — — — — — — — — CCP3 — CWG1C SCL1
(3)
TX CLC3OUT — — — — CWG2C SCL2
(3)
— — — — — — — — — CCP4 — CWG1D SDA1
(3)
— CLC4OUT — — — — CWG2D SDA2
(3) Note 1:
Default peripheral input. Input can be moved to any other pin with the PPS input selection registers.
2:
All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers.
3:
These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4:
These pins are configured for I2C logic levels; clock and data signals may be assigned to any of these pins. Assignments to other pins (e.g. RA5) will operate, but logic levels will be standard TTL/ST as selected by the INLVL register.  2015-2019 Microchip Technology Inc. Document Outline Description Core Features Memory Operating Characteristics eXtreme Low-Power (XLP) Features Power-Saving Functionality Digital Peripherals Analog Peripherals Flexible Oscillator Structure PIC16(L)F183XX Family Types Pin Diagrams Pin Allocation Tables Table of Contents Most Current Data Sheet Errata Customer Notification System Full-Featured, Low Pin Count Microcontrollers with XLP 1.0 Device Overview FIGURE 1-1: PIC16(L)F18325/18345 Block Diagram 2.0 Guidelines for Getting Started With PIC16(L)F183XX Microcontrollers 2.1 Basic Connection Requirements FIGURE 2-1: Recommended Minimum Connections 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.4 ICSP™ Pins 2.5 External Oscillator Pins 2.6 Unused I/Os FIGURE 2-2: Suggested Placement of the Oscillator Circuit 3.0 Enhanced Mid-Range CPU FIGURE 3-1: Core Data Path Block Diagram 3.1 Automatic Interrupt Context Saving 3.2 16-Level Stack with Overflow and Underflow 3.3 File Select Registers 3.4 Instruction Set 4.0 Memory Organization 4.1 Program Memory Organization FIGURE 4-1: Program Memory Map and Stack for PIC16(L)F18325/18345 EXAMPLE 4-1: RETLW Instruction EXAMPLE 4-2: Accessing Program Memory Via FSR 4.2 Data Memory Organization FIGURE 4-2: Banked Memory Partitioning 4.3 PCL and PCLATH FIGURE 4-3: Loading of PC in Different Situations 4.4 Stack FIGURE 4-4: Accessing the Stack Example 1 FIGURE 4-5: Accessing the Stack Example 2 FIGURE 4-6: Accessing the Stack Example 3 FIGURE 4-7: Accessing the Stack Example 4 4.5 Indirect Addressing FIGURE 4-8: Indirect Addressing FIGURE 4-9: Traditional/Banked Data Memory Map FIGURE 4-10: Linear Data Memory Map FIGURE 4-11: Program Flash Memory Map 5.0 Device Configuration 5.1 Configuration Words 5.2 Register Definitions: Configuration Words 5.3 Code Protection 5.4 Write Protection 5.5 User ID 5.6 Device ID and Revision ID 5.7 Register Definitions: Device and Revision 6.0 Resets FIGURE 6-1: Simplified Block Diagram of On-Chip Reset Circuit 6.1 Power-on Reset (POR) 6.2 Brown-out Reset (BOR) FIGURE 6-2: Brown-out Situations 6.3 Low-Power Brown-out Reset (LPBOR)(PIC16LF18325/18345 Devices Only) 6.4 MCLR 6.5 Watchdog Timer (WDT) Reset 6.6 RESET Instruction 6.7 Stack Overflow/Underflow Reset 6.8 Programming Mode Exit 6.9 Power-up Timer 6.10 Start-up Sequence FIGURE 6-3: Reset Start-up Sequence 6.11 Determining the Cause of a Reset 6.12 Power Control (PCON0) Register 6.13 Register Definitions: Power Control 7.0 Oscillator Module 7.1 Overview FIGURE 7-1: Simplified PIC® MCU Clock Source Block Diagram 7.2 Clock Source Types FIGURE 7-2: External Clock (EC) Mode Operation FIGURE 7-3: Quartz Crystal Operation (LP, XT or HS Mode) FIGURE 7-4: Ceramic Resonator Operation (XT or HS Mode) FIGURE 7-5: Quartz Crystal Operation (Secondary Oscillator) 7.3 Clock Switching FIGURE 7-6: Clock Switch (CSWHOLD = 0) FIGURE 7-7: Clock Switch (CSWHOLD = 1) FIGURE 7-8: Clock Switch Abandoned 7.4 Fail-Safe Clock Monitor FIGURE 7-9: FSCM Block Diagram FIGURE 7-10: FSCM Timing Diagram 7.5 Register Definitions: Oscillator Control 8.0 Interrupts FIGURE 8-1: Interrupt Logic 8.1 Operation 8.2 Interrupt Latency FIGURE 8-2: Interrupt Latency FIGURE 8-3: INT Pin Interrupt Timing 8.3 Interrupts During Sleep 8.4 INT Pin 8.5 Automatic Context Saving 8.6 Register Definitions: Interrupt Control 9.0 Power-Saving Operation Modes 9.1 DOZE Mode FIGURE 9-1: Doze Mode Operation Example 9.2 IDLE Mode 9.3 Sleep Mode FIGURE 9-2: Wake-up from Sleep through Interrupt 9.4 Register Definitions: Voltage Regulator Control 10.0 Watchdog Timer (WDT) FIGURE 10-1: Watchdog Timer Block Diagram 10.1 Independent Clock Source 10.2 WDT Operating Modes 10.3 Time-out Period 10.4 Clearing the WDT 10.5 Operation During Sleep 10.6 Register Definitions: Watchdog Control 11.0 Nonvolatile Memory (NVM) Control 11.1 Program Flash Memory 11.2 Data EEPROM 11.3 FSR and INDF Access 11.4 NVMREG Access FIGURE 11-1: Program Flash Memory Read Flowchart EXAMPLE 11-1: Program Flash Memory Read FIGURE 11-2: NVM Unlock Sequence Flowchart EXAMPLE 11-2: NVM Unlock Sequence FIGURE 11-3: NVM Erase Flowchart EXAMPLE 11-3: Erasing One Row of Program Flash Memory FIGURE 11-4: Block Writes to Program Flash Memory with 32 Write Latches FIGURE 11-5: Program Flash Memory Write Flowchart EXAMPLE 11-4: Writing to Program Flash Memory FIGURE 11-6: Program Flash Memory Modify Flowchart FIGURE 11-7: Program Flash Memory Verify Flowchart 11.5 Register Definitions: Program Flash Memory Control 12.0 I/O Ports FIGURE 12-1: Generic I/O Port Operation 12.1 I/O Priorities 12.2 PORTA Registers EXAMPLE 12-1: Initializing PORTA 12.3 Register Definitions: PORTA 12.4 PORTB Registers (PIC16(L)F18345 Only) 12.5 Register Definitions: PORTB 12.6 PORTC Registers 12.7 Register Definitions: PORTC 13.0 Peripheral Pin Select (PPS) Module 13.1 PPS Inputs 13.2 PPS Outputs FIGURE 13-1: Simplified PPS Block Diagram 13.3 Bidirectional Pins 13.4 PPSLOCKED Bit EXAMPLE 13-1: PPS Lock/Unlock sequence 13.5 PPS1WAY Bit 13.6 Operation During Sleep 13.7 Effects of a Reset 13.8 Register Definitions: PPS Input Selection 14.0 Peripheral Module Disable 14.1 Disabling a Module 14.2 Enabling a Module 14.3 System Clock Disable 15.0 Interrupt-on-Change 15.1 Enabling the Module 15.2 Individual Pin Configuration 15.3 Interrupt Flags EXAMPLE 15-1: Clearing Interrupt Flags (PORTA Example) 15.4 Operation in Sleep FIGURE 15-1: Interrupt-on-Change Block Diagram (PORTA Example) 15.5 Register Definitions: Interrupt-on-Change Control 16.0 Fixed Voltage Reference (FVR) 16.1 Independent Gain Amplifiers 16.2 FVR Stabilization Period FIGURE 16-1: Voltage Reference Block Diagram 16.3 Register Definitions: FVR Control 17.0 Temperature Indicator Module 17.1 Circuit Operation EQUATION 17-1: Vout Ranges FIGURE 17-1: Temperature Circuit Diagram 17.2 Minimum Operating Vdd 17.3 Temperature Output 17.4 ADC Acquisition Time 18.0 Comparator Module 18.1 Comparator Overview FIGURE 18-1: Single Comparator FIGURE 18-2: Comparator Module Simplified Block Diagram 18.2 Comparator Control 18.3 Comparator Hysteresis 18.4 Timer1 Gate Operation 18.5 Comparator Interrupt 18.6 Comparator Positive Input Selection 18.7 Comparator Negative Input Selection 18.8 Comparator Response Time 18.9 Analog Input Connection Considerations FIGURE 18-3: Analog Input Model 18.10 CWG Auto-shutdown Source 18.11 Operation in Sleep Mode 18.12 Register Definitions: Comparator Control 19.0 Pulse-Width Modulation (PWM) FIGURE 19-1: PWM Output 19.1 Standard PWM Mode FIGURE 19-2: Simplified PWM Block Diagram EQUATION 19-1: PWM Period EQUATION 19-2: Pulse Width EQUATION 19-3: Duty Cycle Ratio EQUATION 19-4: 19.2 Register Definitions: PWM Control 20.0 Complementary Waveform Generator (CWG) Module 20.1 Fundamental Operation 20.2 Operating Modes FIGURE 20-1: CWGx Half-Bridge Mode Operation FIGURE 20-2: CWGx Push-Pull Mode Operation FIGURE 20-3: Example of Synchronous Steering (MODE<2:0> = 001) FIGURE 20-4: Example of Asynchronous Steering (MODE<2:0> = 000) FIGURE 20-5: Example of Full-Bridge Application FIGURE 20-6: Example of Full-Bridge Output FIGURE 20-7: Example of PWM Direction Change at Near 100% Duty Cycle FIGURE 20-8: Simplified CWGx Block Diagram (Half-Bridge Mode, MODE<2:0> = 100) FIGURE 20-9: Simplified CWG Block Diagram (Push-Pull Mode, MODE <2:0> = 101) FIGURE 20-10: Simplified CWG Block Diagram (Output Steering Modes) FIGURE 20-11: Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) 20.3 Clock Source 20.4 Selectable Input Sources 20.5 Output Control 20.6 Dead-Band Control EQUATION 20-1: Dead-Band Delay Time Calculation 20.7 Auto-Shutdown Control 20.8 Auto-Shutdown Restart 20.9 Operation During Sleep 20.10 Configuring the CWG 20.11 Register Definitions: CWG Control 21.0 Configurable Logic Cell (CLC) FIGURE 21-1: CLCx Simplified Block Diagram 21.1 CLCx Setup 21.2 CLCx Interrupts 21.3 Output Mirror Copies 21.4 Effects of a Reset 21.5 Operation During Sleep 21.6 CLCx Setup Steps FIGURE 21-2: Input Data Selection and Gating FIGURE 21-3: Programmable Logic Functions 21.7 Register Definitions: CLC Control 22.0 Analog-to-Digital Converter (ADC) Module FIGURE 22-1: ADC Block Diagram 22.1 ADC Configuration FIGURE 22-2: Analog-to-Digital Conversion Tad Cycles FIGURE 22-3: 10-bit ADC Conversion Result Format 22.2 ADC Operation EXAMPLE 22-1: ADC Conversion 22.3 ADC Acquisition Requirements EQUATION 22-1: Acquisition Time Example FIGURE 22-4: Analog Input Model FIGURE 22-5: ADC Transfer Function 22.4 Register Definitions: ADC Control 23.0 Numerically Controlled Oscillator (NCO1) Module FIGURE 23-1: Numerically Controlled Oscillator Module Simplified Block Diagram 23.1 NCO1 Operation EQUATION 23-1: NC01 Overflow Frequency 23.2 Fixed Duty Cycle (FDC) Mode EQUATION 23-2: FDC Frequency 23.3 Pulse Frequency (PF) Mode 23.4 Output Polarity Control FIGURE 23-2: FDC Output Mode Operation Diagram 23.5 Interrupts 23.6 Effects of a Reset 23.7 Operation in Sleep 23.8 NCO1 Control Registers 24.0 5-bit Digital-to-Analog Converter (DAC1) Module 24.1 Output Voltage Selection EQUATION 24-1: DAC Output Voltage 24.2 Ratiometric Output Level 24.3 DAC Voltage Reference Output FIGURE 24-1: Digital-to-Analog Converter Block Diagram FIGURE 24-2: Voltage Reference Output Buffer Example 24.4 Operation During Sleep 24.5 Effects of a Reset 24.6 Register Definitions: DAC Control 25.0 Data Signal Modulator (DSM) Module FIGURE 25-1: Simplified Block Diagram of the Data Signal Modulator 25.1 DSM Operation 25.2 Modulator Signal Sources 25.3 Carrier Signal Sources 25.4 Carrier Synchronization FIGURE 25-2: On Off Keying (OOK) Synchronization FIGURE 25-3: No Synchronization (MDSHSYNC = 0, MDCLSYNC = 0) FIGURE 25-4: Carrier High Synchronization (MDSHSYNC = 1, MDCLSYNC = 0) FIGURE 25-5: Carrier Low Synchronization (MDSHSYNC = 0, MDCLSYNC = 1) FIGURE 25-6: Full Synchronization (MDSHSYNC = 1, MDCLSYNC = 1) 25.5 Carrier Source Polarity Select 25.6 Programmable Modulator Data 25.7 Modulated Output Polarity 25.8 Slew Rate Control 25.9 Operation in Sleep Mode 25.10 Effects of a Reset 25.11 Register Definitions: Modulation Control 26.0 Timer0 Module 26.1 Timer0 Operation 26.2 Clock Source Selection 26.3 Programmable Prescaler 26.4 Programmable Postscaler 26.5 Operation During Sleep 26.6 Timer0 Interrupts 26.7 Timer0 Output FIGURE 26-1: Block Diagram of Timer0 26.8 Register Definitions: Timer0 Register 27.0 Timer1/3/5 Module with Gate Control FIGURE 27-1: Timer1 Block Diagram 27.1 Timer1 Operation 27.2 Clock Source Selection 27.3 Timer1 Prescaler 27.4 Timer1 Operation in Asynchronous Mode 27.5 Timer1 Gate 27.6 Timer1 Interrupt 27.7 Timer1 Operation During Sleep 27.8 CCP Capture/Compare Time Base 27.9 CCP Auto-Conversion Trigger FIGURE 27-2: Timer1 Incrementing Edge FIGURE 27-3: Timer1 Gate Enable Mode FIGURE 27-4: Timer1 Gate Toggle Mode FIGURE 27-5: Timer1 Gate Single-Pulse Mode FIGURE 27-6: Timer1 Gate Single-Pulse and Toggle Combined Mode 27.10 Register Definitions: Timer1/3/5 Control 28.0 Timer2/4/6 Module FIGURE 28-1: Timer2/4/6 Block Diagram 28.1 Timer2 Operation 28.2 Timer2 Interrupt 28.3 Timer2 Output 28.4 Timer2 Operation During Sleep 28.5 Register Definitions: Timer2/4/6 Control 29.0 Capture/Compare/PWM Modules 29.1 CCP/PWM Clock Selection 29.2 Capture Mode FIGURE 29-1: Capture Mode Operation Block Diagram EXAMPLE 29-1: Changing Between Capture Prescalers 29.3 Compare Mode FIGURE 29-2: Compare Mode Operation Block Diagram 29.4 PWM Overview FIGURE 29-3: CCP PWM Output Signal FIGURE 29-4: Simplified PWM Block Diagram EQUATION 29-1: PWM Period FIGURE 29-5: PWM 10-bit Alignment Block Diagram EQUATION 29-2: Pulse Width EQUATION 29-3: Duty Cycle Ratio EQUATION 29-4: PWM Resolution 29.5 Register Definitions: CCP Control 30.0 Master Synchronous Serial Port (MSSPx) Module 30.1 MSSPx Module Overview FIGURE 30-1: MSSP Block Diagram (SPI mode) FIGURE 30-2: MSSP Block Diagram (I2C Master mode) FIGURE 30-3: MSSP Block Diagram (I2C Slave mode) 30.2 SPI Mode Overview FIGURE 30-4: SPI Master and Multiple Slave Connection FIGURE 30-5: SPI Master/Slave Connection FIGURE 30-6: SPI Mode Waveform (Master Mode) FIGURE 30-7: SPI Daisy-Chain Connection FIGURE 30-8: Slave Select Synchronous Waveform FIGURE 30-9: SPI Mode Waveform (Slave Mode with CKE = 0) FIGURE 30-10: SPI Mode Waveform (Slave Mode with CKE = 1) 30.3 I2C Mode Overview FIGURE 30-11: I2C Master/ Slave Connection 30.4 I2C Mode Operation FIGURE 30-12: I2C Start and Stop Conditions FIGURE 30-13: I2C Restart Condition 30.5 I2C Slave Mode Operation FIGURE 30-14: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 30-15: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 30-16: I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) FIGURE 30-17: I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 30-18: I2C Slave, 7-bit Address, Transmission (AHEN = 0) FIGURE 30-19: I2C Slave, 7-bit Address, Transmission (AHEN = 1) FIGURE 30-20: I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 30-21: I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 30-22: I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) FIGURE 30-23: Clock Synchronization Timing FIGURE 30-24: Slave Mode General Call Address Sequence 30.6 I2C Master Mode FIGURE 30-25: Baud Rate Generator Timing with Clock Arbitration FIGURE 30-26: First Start Bit Timing FIGURE 30-27: Repeated Start Condition Waveform FIGURE 30-28: I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) FIGURE 30-29: I2C Master Mode Waveform (Reception, 7-bit Address) FIGURE 30-30: Acknowledge Sequence Waveform FIGURE 30-31: Stop Condition Receive or Transmit Mode FIGURE 30-32: Bus Collision Timing for Transmit and Acknowledge FIGURE 30-33: Bus Collision During Start Condition (SDA Only) FIGURE 30-34: Bus Collision During Start Condition (SCL = 0) FIGURE 30-35: BRG Reset Due to SDA Arbitration During Start Condition FIGURE 30-36: Bus Collision During a Repeated Start Condition (Case 1) FIGURE 30-37: Bus Collision During Repeated Start Condition (Case 2) FIGURE 30-38: Bus Collision During a Stop Condition (Case 1) FIGURE 30-39: Bus Collision During a Stop Condition (Case 2) 30.7 Baud Rate Generator FIGURE 30-40: Baud Rate Generator Block Diagram 30.8 Register Definitions: MSSP Control 31.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART1) FIGURE 31-1: EUSART1 Transmit Block Diagram FIGURE 31-2: EUSART1 Receive Block Diagram 31.1 EUSART1 Asynchronous Mode FIGURE 31-3: Asynchronous Transmission FIGURE 31-4: Asynchronous Transmission (Back-to-Back) FIGURE 31-5: Asynchronous Reception 31.2 Clock Accuracy with Asynchronous Operation 31.3 EUSART1 Baud Rate Generator (BRG) EXAMPLE 31-1: Calculating Baud Rate Error FIGURE 31-6: Automatic Baud Rate Calibration FIGURE 31-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation FIGURE 31-8: Auto-Wake-up Bit (WUE) Timings During Sleep FIGURE 31-9: Send Break Character Sequence 31.4 EUSART1 Synchronous Mode FIGURE 31-10: Synchronous Transmission FIGURE 31-11: Synchronous Transmission (through TXEN) FIGURE 31-12: Synchronous Reception (Master Mode, SREN) 31.5 EUSART1 Operation During Sleep 31.6 Register Definitions: EUSART1 Control 32.0 Reference Clock Output Module 32.1 Clock Source 32.2 Programmable Clock Divider 32.3 Selectable Duty Cycle 32.4 Operation in Sleep Mode FIGURE 32-1: Clock Reference Block Diagram FIGURE 32-2: Clock Reference Timing 33.0 In-Circuit Serial Programming™ (ICSP™) 33.1 High-Voltage Programming Entry Mode 33.2 Low-Voltage Programming Entry Mode 33.3 Common Programming Interfaces FIGURE 33-1: ICD RJ-11 Style Connector Interface FIGURE 33-2: PICkit™ Programmer Style Connector Interface FIGURE 33-3: Typical Connection for ICSP™ Programming 34.0 Instruction Set Summary 34.1 Read-Modify-Write Operations FIGURE 34-1: General Format for Instructions 34.2 Instruction Descriptions 35.0 Electrical Specifications 35.1 Absolute Maximum Ratings(†) 35.2 Standard Operating Conditions FIGURE 35-1: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16F18325/18345 Only FIGURE 35-2: Voltage Frequency Graph, -40°C £ Ta £ +125°C, PIC16LF18325/18345 Only 35.3 DC Characteristics FIGURE 35-3: POR and POR ReARM with Slow Rising Vdd 35.4 AC Characteristics FIGURE 35-4: Load Conditions FIGURE 35-5: Clock Timing FIGURE 35-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device Vdd and Temperature FIGURE 35-7: CLKOUT and I/O Timing FIGURE 35-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing FIGURE 35-9: Brown-out Reset Timing and Characteristics FIGURE 35-10: ADC Conversion Timing (ADC Clock Fosc-Based) FIGURE 35-11: ADC Conversion Timing (ADC Clock from ADCRC) FIGURE 35-12: Timer0 and Timer1 External Clock Timings FIGURE 35-13: Capture/Compare/PWM (CCP) Timings FIGURE 35-14: CLC Propagation Timing FIGURE 35-15: EUSART Synchronous Transmission (Master/Slave) Timing FIGURE 35-16: EUSART Synchronous Receive (Master/Slave) Timing FIGURE 35-17: SPI Master Mode Timing (CKE = 0, SMP = 0) FIGURE 35-18: SPI Master Mode Timing (CKE = 1, SMP = 1) FIGURE 35-19: SPI Slave Mode Timing (CKE = 0) FIGURE 35-20: SPI Slave Mode Timing (CKE = 1) FIGURE 35-21: I2C Bus Start/Stop Bits Timing FIGURE 35-22: I2C Bus Data Timing 36.0 DC and AC Characteristics Graphs and Charts 37.0 Development Support 37.1 MPLAB X Integrated Development Environment Software 37.2 MPLAB XC Compilers 37.3 MPASM Assembler 37.4 MPLINK Object Linker/ MPLIB Object Librarian 37.5 MPLAB Assembler, Linker and Librarian for Various Device Families 37.6 MPLAB X SIM Software Simulator 37.7 MPLAB REAL ICE In-Circuit Emulator System 37.8 MPLAB ICD 3 In-Circuit Debugger System 37.9 PICkit 3 In-Circuit Debugger/ Programmer 37.10 MPLAB PM3 Device Programmer 37.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits 37.12 Third-Party Development Tools 38.0 Packaging Information 38.1 Package Marking Information Package Marking Information (Continued) Package Marking Information (Continued) 38.2 Package Details Appendix A: Data Sheet Revision History The Microchip WebSite Customer Change Notification Service Customer Support Product Identification System Trademarks Worldwide Sales and Service