PIC16(L)F1885X/7X PIN DIAGRAMS Pin Diagram – 28-Pin (S)PDIP, SOIC, SSOP 2 RA1 3 RA2 4 RA3 5 RA4 6 RA5 VSS 7 RA7 9 RA6 10 RC0 11 RC1 12 RC2 13 RC3 Note 1: 2: 1 RA0 PIC16(L)F18854/18855/18856/18857 VPP/MCLR/RE3 8 14 28 RB7 27 RB6 26 RB5 25 RB4 24 23 RB3 22 21 RB1 RB0 20 VDD 19 18 VSS RC7 17 RC6 16 RC5 15 RC4 RB2 See Table 3 for location of all peripheral functions. All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float may result in degraded electrical performance or non-functionality. 28 27 26 25 24 23 22 RA1 RA0 RE3/MCLR/VPP RB7 RB6 RB5 RB4 Pin Diagram – 28-Pin UQFN (4x4) (except for PIC16F18857) and QFN (6x6) 16 8 18 )F (L 75 8 /1 87 18 6/ 87 RC0 8 RC1 9 RC2 10 RC3 11 RC4 12 RC5 13 RC6 14 7 1 2 3 4 5 6 7 C PI RA2 RA3 RA4 RA5 VSS RA7 RA6 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 Note 1: See Table 3 for location of all peripheral functions. 2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to float may result in degraded electrical performance or non-functionality. 3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level. DS40001768A-page 4 Advance Information 2014 Microchip Technology Inc.