Datasheet 24C01C (Microchip) - 6

HerstellerMicrochip
Beschreibung1K 5.0V I2C Serial EEPROM
Seiten / Seite36 / 6 — 24C01C. 3.0. FUNCTIONAL DESCRIPTION. 4.4. Data Valid (D). 4.0. BUS …
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24C01C. 3.0. FUNCTIONAL DESCRIPTION. 4.4. Data Valid (D). 4.0. BUS CHARACTERISTICS. bus protocol. 4.5. Acknowledge. Note:. 4.1

24C01C 3.0 FUNCTIONAL DESCRIPTION 4.4 Data Valid (D) 4.0 BUS CHARACTERISTICS bus protocol 4.5 Acknowledge Note: 4.1

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24C01C 3.0 FUNCTIONAL DESCRIPTION 4.4 Data Valid (D)
The 24C01C supports a bidirectional 2-wire bus and The state of the data line represents valid data when, data transmission protocol. A device that sends data after a Start condition, the data line is stable for the onto the bus is defined as transmitter, and a device duration of the high period of the clock signal. receiving data as receiver. The bus has to be controlled The data on the line must be changed during the low by a master device that generates the Serial Clock period of the clock signal. There is one bit of data per (SCL), controls the bus access, and generates the Start clock pulse. and Stop conditions, while the 24C01C works as slave. Both master and slave can operate as transmitter or Each data transfer is initiated with a Start condition and receiver, but the master device determines which mode terminated with a Stop condition. The number of the is activated. data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited, although only the last sixteen
4.0 BUS CHARACTERISTICS
wil be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in first- The following
bus protocol
has been defined: out fashion. • Data transfer may be initiated only when the bus is not busy.
4.5 Acknowledge
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in Each receiving device, when addressed, is required to the data line while the clock line is high wil be generate an acknowledge after the reception of each interpreted as a Start or Stop condition. byte. The master device must generate an extra clock pulse, which is associated with this Acknowledge bit. Accordingly, the following bus conditions have been defined (Figure 4-1).
Note:
The 24C01C does not generate any Acknowledge bits if an internal program-
4.1 Bus Not Busy (A)
ming cycle is in progress. Both data and clock lines remain high. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a
4.2 Start Data Transfer (B)
way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of A high-to-low transition of the SDA line while the clock course, setup and hold times must be taken into (SCL) is high determines a Start condition. All account. A master must signal an end of data to the commands must be preceded by a Start condition. slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case,
4.3 Stop Data Transfer (C)
the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. DS21201K-page 6  1997-2012 Microchip Technology Inc. Document Outline 24C01C Features: Description: Block Diagram Package Types 1.0 Electrical Characteristics Absolute Maximum Ratings(†) TABLE 1-1: DC Characteristics TABLE 1-2: AC Characteristics FIGURE 1-1: Bus Timing Data 2.0 Pin Descriptions TABLE 2-1: Pin Function Table 2.1 SDA Serial Data 2.2 SCL Serial Clock 2.3 A0, A1, A2 2.4 Test 2.5 Noise Protection 3.0 Functional Description 4.0 Bus Characteristics 4.1 Bus Not Busy (A) 4.2 Start Data Transfer (B) 4.3 Stop Data Transfer (C) 4.4 Data Valid (D) 4.5 Acknowledge FIGURE 4-1: Data Transfer Sequence on the Serial Bus FIGURE 4-2: Acknowledge Timing 5.0 Device Addressing FIGURE 5-1: Control Byte Format 5.1 Contiguous Addressing Across Multiple Devices 6.0 Write Operations 6.1 Byte Write 6.2 Page Write FIGURE 6-1: Byte Write FIGURE 6-2: Page Write 7.0 Acknowledge Polling FIGURE 7-1: Acknowledge Polling Flow 8.0 Read Operation 8.1 Current Address Read FIGURE 8-1: Current Address Read 8.2 Random Read 8.3 Sequential Read FIGURE 8-2: Random Read FIGURE 8-3: Sequential Read 9.0 Packaging Information 9.1 Package Marking Information Appendix A: Revision History The Microchip Web Site Customer Change Notification Service Customer Support Reader Response Product Identification System Trademarks Worldwide Sales