Datasheet AD7711A (Analog Devices) - 8

AD7711A Pin Mnemonic Function
19 TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active after TFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is written to the part. 20 RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, both the SCLK and SDATA lines become active after RFS goes low. In the external clocking mode, the SDATA line becomes active after RFS goes low. 21 DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate when the AD7711A has completed its on-chip calibration sequence. 22 SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration registers and serial data being accessed from the control register, calibration registers, or the data register. During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low). During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. The output data coding is natural binary for unipolar inputs and offset binary for bipolar inputs. 23 DVDD Digital Supply Voltage, 5 V. DVDD should not exceed AVDD by more than 0.3 V in normal operation. 24 DGND Ground Reference Point for Digital Circuitry.
TERMINOLOGY Positive Full-Scale Overrange
Positive full-scale overrange is the amount of overhead available
Integral Nonlinearity
to handle input voltages on AIN(+) input greater than AIN(–) + This is the maximum deviation of any code from a straight line V passing through the endpoints of the transfer function. The end- REF/GAIN (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without intro- points of the transfer function are zero scale (not to be confused ducing errors due to overloading the analog modulator or over- with bipolar zero), a point 0.5 LSB below the first code transition flowing the digital filter. (000 . 000 to 000 . 001) and full scale, a point 0.5 LSB above the last code transition (111 . 110 to 111 . 111). The
Negative Full-Scale Overrange
error is expressed as a percentage of full scale. This is the amount of overhead available to handle voltages on AIN(+) below AIN(–) – V
Positive Full-Scale Error
REF/GAIN without overloading the analog modulator or overflowing the digital filter. Note that the Positive full-scale error is the deviation of the last code transi- analog input will accept negative voltage peaks even in the uni- tion (111 . 110 to 111 . 111) from the ideal AIN(+) voltage polar mode provided that AIN(+) is greater than AIN(–) and (AIN(–) + VREF/GAIN – 3/2 LSBs). It applies to both unipolar greater than V and bipolar analog input ranges. SS – 30 mV.
Offset Calibration Range Unipolar Offset Error
In the system calibration modes, the AD7711A calibrates its Unipolar offset error is the deviation of the first code transition offset with respect to the analog input. The offset calibration from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper- range specification defines the range of voltages that the ating in the unipolar mode. AD7711A can accept and still accurately calibrate offset.
Bipolar Zero Error Full-Scale Calibration Range
This is the deviation of the midscale transition (0111 . 111 This is the range of voltages that the AD7711A can accept in to 1000 . 000) from the ideal AIN(+) voltage (AIN(–) the system calibration mode and still correctly calibrate full scale. – 0.5 LSB) when operating in the bipolar mode.
Input Span Bipolar Negative Full-Scale Error
In system calibration schemes, two voltages applied in sequence This is the deviation of the first code transition from the ideal to the AD7711A’s analog input define the analog input range. AIN(+) voltage (AIN(–) – VREF/GAIN + 0.5 LSB) when operat- The input span specification defines the minimum and maxi- ing in the bipolar mode. mum input voltages from zero scale to full scale that the AD7711A can accept and still calibrate accurately gain. –8– REV. D