Datasheet TB67S112PG (Toshiba) - 3

TB67S112PG
Block Diagram
VM VCC COM regulator ERR TSD UVLO ISD OUT1 IN1 Control Logic ISD OUT2 IN2 GND Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes.
IC considerations
When using TB67S112PG, the GND pattern of PCB should be a solid pattern and be externally terminated at only one point. Also, a grounding method should be considered for efficient heat dissipation. Careful attention should be paid to the layout of the output, VM, COM, and GND traces, to avoid short circuits across output pins or to the power supply or ground. If such a short circuit occurs, the device may be permanently damaged. Also, the utmost care should be taken for pattern designing and implementation of the device since it has power supply pins (VM, COM, OUT1, OUT2, and GND) through which a particularly large current may run. If these pins are wired incorrectly, an operation error may occur or the device may be destroyed. The logic input pins must also be wired correctly. Otherwise, the device may be damaged owing to a current running through the IC that is larger than the specified current. Careful attention should be paid to design patterns and mountings. 3 2019-07-08