Datasheet IR3826 (Infineon) - 7

IR 8 OptiMOS™ IPOL 23 A single-voltage synchronous Buck regulator Pin descriptions 4 Pin descriptions Table 2 Pin descriptions Pin# Pin name Pin description
1 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 2 NC Not Connected 3 Comp Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb to provide loop compensation. 4 Gnd Signal ground for internal reference and control circuitry. 5 Rt Set switching frequency. Use an external resistor from this pin to Gnd to set the free-running switching frequency. 6 ILIM Current Limit set point. This pin allows the trip point to be set to one of three possible settings by floating this pin, connecting it to Vcc or connecting it to PGnd. 7 PGood Power Good status pin. Connect a pull up resistor from this open drain output to a voltage lower than or equal to the Vcc supply. 8 Vsns Sense pin for over-voltage protection and PGood. 9 Vin Input voltage for Internal LDO. A 1.0 µF capacitor should be connected between this pin and PGnd. If an external supply is connected to Vcc/LDO_out pin, this pin should be shorted to Vcc/LDO_out pin. 10 Vcc/LDO_Out Input Bias for external Vcc Voltage/ output of internal LDO. Place a 2.2 µF capacitor from this pin to PGnd. 11 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 12 SW Switch node. This pin is connected to the output inductor. 13 PVin Input voltage for power stage. 14 Boot Supply voltage for the high side driver, a 100 nF capacitor should be connected between this pin and SW pin. 15 Enable Enable pin to turn the device on and off. Connecting this pin to PVin pin through a resistor divider implements the input voltage UVLO function. 16 NC Not Connected 17 Gnd Signal ground for internal reference and control circuitry. Final Datasheet 7 of 53 V2.4 June 28 2019 Document Outline Revision History Trademarks Disclaimer