Datasheet TMD2635 (AustriaMicroSystems) - 10
| Hersteller | AustriaMicroSystems |
| Beschreibung | Miniature Proximity Sensor Module |
| Seiten / Seite | 47 / 10 — TMD2635 −. Figure 11: I²C Schemes. Figure 12: I²C Address Selection. … |
| Dateiformat / Größe | PDF / 707 Kb |
| Dokumentensprache | Englisch |
TMD2635 −. Figure 11: I²C Schemes. Figure 12: I²C Address Selection. Master I²C Bus Signal. Clock. Data. 7-Bit I²C Address
Modelllinie für dieses Datenblatt
Textversion des Dokuments
TMD2635 −
Detailed Description
Figure 11: I²C Schemes
SCL clock TMD2635 SDA (0x39) data SCL TMD2635 SDA (0x38)
Figure 12: I²C Address Selection Master I²C Bus Signal Clock Data 7-Bit I²C Address
SCL SDA 0x39 SDA SCL 0x38
I²C Write Transaction
A write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, DATA BYTE(S), and STOP. Following each byte (9th clock pulse) the slave places an ACKNOWLEDGE/ NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP.
I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, START, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the master places an ACK on the bus (9th clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP. Alternately, if the previous I²C transaction was a read, the internal register address buffer is still valid, allowing the transaction to proceed without “re”-specifying the register address. In this case the transaction consists of a START, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but
Page 10 ams Datasheet
Document Feedback [v1-00] 2019-Jul-17 Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignment Absolute Maximum Ratings Electrical Characteristics Timing Characteristics Detailed Description Proximity Operation Proximity I²C Characteristics Alternate I²C Address Option I²C Write Transaction I²C Read Transaction Simplified State Diagram Register Description ENABLE Register (0x80) PRATE Register (0x82) PILTL Register (0x88) PILTH Register (0x89) PIHTL Register (0x8A) PIHTH Register (0x8B) PERS Register (0x8C) CFG0 Register (0x8D) PCFG0 Register (0x8E) PCFG1 Register (0x8F) REVID Register (0x91) ID Register (0x92) STATUS Register (0x9B) PDATAL Register (0x9C) PDATAH Register (0x9D) REVID2 Register (0xA6) SOFTRST Register (0xA8) PWTIME Register (0xA9) CFG8 Register (0xAA) CFG3 Register (0xAB) CFG6 Register (0xAE) PFILTER Register (0xB3) POFFSETL Register (0xC0) POFFSETH Register (0xC1) CALIB Register (0xD7) CALIBCFG Register (0xD9) CALIBSTAT Register (0xDC) INTENAB Register (0xDD) FAC_L Register (0xE5) FAC_H Register (0xE6) TEST9 Register (0xF9) Application Information PCB Pad Layout Packaging Drawings Tape & Reel Information Soldering & Storage Information Storage Information Moisture Sensitivity Shelf Life Floor Life Rebaking Instructions Laser Eye Safety Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide
Detailed Description
Figure 11: I²C Schemes
SCL clock TMD2635 SDA (0x39) data SCL TMD2635 SDA (0x38)
Figure 12: I²C Address Selection Master I²C Bus Signal Clock Data 7-Bit I²C Address
SCL SDA 0x39 SDA SCL 0x38
I²C Write Transaction
A write transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, DATA BYTE(S), and STOP. Following each byte (9th clock pulse) the slave places an ACKNOWLEDGE/ NOT-ACKNOWLEDGE (ACK/NACK) on the bus. If NACK is transmitted by the slave, the master may issue a STOP.
I²C Read Transaction
A Read transaction consists of a START, CHIP-ADDRESSWRITE, REGISTER-ADDRESS, START, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but the final byte the master places an ACK on the bus (9th clock pulse). Termination of the Read transaction is indicated by a NACK being placed on the bus by the master, followed by STOP. Alternately, if the previous I²C transaction was a read, the internal register address buffer is still valid, allowing the transaction to proceed without “re”-specifying the register address. In this case the transaction consists of a START, CHIP-ADDRESSREAD, DATA BYTE(S), and STOP. Following all but
Page 10 ams Datasheet
Document Feedback [v1-00] 2019-Jul-17 Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignment Absolute Maximum Ratings Electrical Characteristics Timing Characteristics Detailed Description Proximity Operation Proximity I²C Characteristics Alternate I²C Address Option I²C Write Transaction I²C Read Transaction Simplified State Diagram Register Description ENABLE Register (0x80) PRATE Register (0x82) PILTL Register (0x88) PILTH Register (0x89) PIHTL Register (0x8A) PIHTH Register (0x8B) PERS Register (0x8C) CFG0 Register (0x8D) PCFG0 Register (0x8E) PCFG1 Register (0x8F) REVID Register (0x91) ID Register (0x92) STATUS Register (0x9B) PDATAL Register (0x9C) PDATAH Register (0x9D) REVID2 Register (0xA6) SOFTRST Register (0xA8) PWTIME Register (0xA9) CFG8 Register (0xAA) CFG3 Register (0xAB) CFG6 Register (0xAE) PFILTER Register (0xB3) POFFSETL Register (0xC0) POFFSETH Register (0xC1) CALIB Register (0xD7) CALIBCFG Register (0xD9) CALIBSTAT Register (0xDC) INTENAB Register (0xDD) FAC_L Register (0xE5) FAC_H Register (0xE6) TEST9 Register (0xF9) Application Information PCB Pad Layout Packaging Drawings Tape & Reel Information Soldering & Storage Information Storage Information Moisture Sensitivity Shelf Life Floor Life Rebaking Instructions Laser Eye Safety Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide