Datasheet AD8304 (Analog Devices) - 10

AD8304 1.6
is thus 4.0 V, which can be accommodated by the rail-to-rail output stage when using the recommended 5 V supply. The capacitor from VLOG to ground forms an optional single-
1.2
pole low-pass filter. Since the resistance at this pin is trimmed to 5 kΩ, an accurate time constant can be realized. For ex-
V
ample, with CFLT = 10 nF, the –3 dB corner frequency is
– 0.8
3.2 kHz. Such filtering is useful in minimizing the output noise,
LOGV
particularly when IPD is small. Multipole filters are more effec- tive in reducing noise, and are discussed below. A capacitor between VSUM and ground is essential for minimizing the
0.4
noise on this node. When the bias voltage at either VPDB or VREF is not needed these pins should be left unconnected.
Slope and Intercept Adjustments 0 100p 1n 10n 100n 1 10 100 1m 10m
The choice of slope and intercept depends on the application.
INPUT – A
The versatility of the AD8304 permits optimal choices to be Figure 2. Ideal Form of V made in two common situations. First, it allows an input current LOG vs. IPD range of less than the full 160 dB to use the available voltage span Using a value of 0.3 pF for CJ evaluates to 20 MHz/mA. There- at the output. Second, it allows this output voltage range to be fore, the minimum bandwidth at IPD = 100 pA would be 2 kHz. optimally positioned to fit the input capacity of a subsequent While this simple model is useful in making a point, it excludes ADC. In special applications, very high slopes, such as 1 V/dec, other effects that limit its usefulness. For example, the network allow small subranges of I R1, C1 in Figure 1, which is necessary to stabilize the system over PD to be covered at high sensitivity. the full range of currents, affects bandwidth at all values of I The slope can be lowered without limit by the addition of a PD. Later signal processing blocks also limit the maximum value. shunt resistor, RS, from VLOG to ground. Since the resistance at this pin is trimmed to 5 kΩ, the accuracy of the modified TPC 7 shows ac response curves for the AD8304 at eight repre- slope will depend on the external resistor. It is calculated using: sentative currents of 100 pA to 10 mA, using R1 = 750 Ω and C1 = 1000 pF. The values for R1 and C1 ensure stability over V R Y S the full 160 dB dynamic range. More optimal values may be used V = Y R' +5 kΩ (15) S for smaller subranges. A certain amount of experimental trial and error may be necessary to select the optimum input network
VP
component values for a given application.
VPS2 PWDN VPS1 10 2 12
Turning now to the noise performance of a translinear log amp,
I
the relationship between I
PD
PD and the voltage noise spectral density, S
PDB BIAS VREF 7 VREF
NSD, associated with the VBE of Q1, evaluates to the following:
VPDB NC ~10k 0.5V 200mV/DEC
S = 14 7 . NSD (14)
VSUM CFLT
I
3 VLOG
PD
8 INPT 4
where S
5k
NSD is nV/Hz, IPD is expressed in microamps and TA = 25°C.
BFIN 9
For an input of 1 nA, S
VSUM TEMPERATURE C1 RB
NSD evaluates to almost 0.5 µV/√Hz; assum-
5 COMPENSATION 1nF BFNG 10k
ing a 20 kHz bandwidth at this current, the integrated noise
13 10nF
voltage is 70 µV rms. However, the calculation is not complete.
R1
The basic scaling of the V
RA
BE is approximately 3 mV/dB; translated
750 15k
to 10 mV/dB, the noise predicted by Equation 14 must be multi- plied by approximately 3.33. The additive noise effects associated
1 14 11 VNEG ACOM VOUT
with the reference transistor, Q2, and the temperature compen-
NC = NO CONNECT VOUT
sation circuitry must also be included. The final voltage noise
500mV/DEC
spectral density presented at the VLOG Pin varies inversely with Figure 3. Basic Connections (RA, RB, CFLT are IPD, but not as simple as square root. TPCS 8 and 9 show the optional; R1 and C1 are the default values) measured noise spectral density versus frequency at the VLOG output, for the same nine-decade spaced values of IPD. For example, using R
Chip Enable
S = 3 kΩ, the slope is lowered to 75 mV per decade or 3.75 mV/dB. Table I provides a selection of suitable The AD8304 may be powered down by taking the PWDN Pin values for R to a high logic level. The residual supply current in the disabled S and the resulting slopes. mode is typically 60 µA.
Table I. Examples of Lowering the Slope USING THE AD8304 RS (k ) VY (mV/dec)
The basic connections (Figure 3) include a 2.5:1 attenuator in the feedback path around the buffer. This increases the basic slope 3 75 of 10 mV/dB at the VLOG Pin to 25 mV/dB at V 5 100 OUT. For the full dynamic range of 160 dB (80 dB optical), the output swing 15 150 –10– REV. A Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS ORDERING GUIDE Typical Performance Characteristics BASIC CONCEPTS Optical Measurements Decibel Scaling GENERAL STRUCTURE Bandwidth and Noise Considerations Chip Enable USING THE AD8304 Slope and Intercept Adjustments Low Supply Slope and Intercept Adjustment Using the Adaptive Bias Changing the Voltage at the Summing Node Implementing Low-Pass Filters Operation in Comparator Modes Using a Negative Supply APPLICATIONS Summing Node at Ground and Voltage Inputs Providing Negative Outputs and Rescaling Inverting the Slope Programmable Level Comparator with Hysteresis Programmable Multidecade Current Source Characterization Setups and Methods Evaluation Board OUTLINE DIMENSIONS Revision History