Datasheet ADL5315 (Analog Devices) - 9

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Data Sheet ADL5315 THEORY OF OPERATION
The ADL5315 addresses the need for precision high-side The ADL5315 provides a setpoint reference pin, SREF, monitoring of photodiode current in fiber optic systems and is which can be connected to VSET for standard 2-port useful in many nonoptical applications as well. It is optimized mirror operation. VSREF is maintained 1.0 V below VPOS over for use with ADI’s family of translinear logarithmic amplifiers, temperature and is independent of input current. When using which take advantage of the wide input current range of the SREF to set the input voltage, a capacitor should be placed ADL5315. This arrangement al ows the anode of the photo- between SREF and ground to filter noise from SREF as well diode to connect directly to a transimpedance amplifier for the as improve power supply rejection over frequency. A value of extraction of the data stream without the need for a separate 2.2 nF, for example, combined with the 20 kΩ output resistance optical power monitoring tap. Figure 19 shows the basic at SREF, creates a pole at approximately 3 kHz. connections for the ADL5315. The voltage at the SREF pin can be lowered to a desired fixed
ADL5315
value with the use of a single external resistor from SREF to
4 COMM RLIM 5
ground. Mismatch between on-chip and external resistors
RLIM
limits the accuracy of the resultant voltage. In addition, internal
VOLTAGE 3 SREF VPOS 6 SUPPLY
clamping to protect the precision bias limits the range. Figure 20
2.2nF 0.1
µ
F 0.01
µ
F
shows an equivalent circuit model of the SREF biasing. The
2 VSET NC 7
Schottky diode clamp protects the 50 µA current source when SREF is pulled to ground. When VSREF is 1.2 V or higher, the
1 INPT IOUT 8 MIRROR
50 µA current flows to the SREF pin. The current is shunted
4k
Ω
CURRENT OUTPUT
away and does not appear at the SREF pin for V
390pF
SREF < 0.6 V. The transition region is between 0.6 V and 1.2 V with a large 05694-023 Figure 19. Basic Connections uncertainty in the pul -down current. It is recommended that a 2-resistor divider from VPOS (with no connection to SREF) or At the heart of the ADL5315 is a precision 1:1 current another external bias be used to bias VREF in this transition mirror with a voltage fol owing characteristic that provides an region. adjustable bias voltage at the mirror input. This architecture uses a JFET input amplifier to drive the bipolar mirror and Equations for the SREF voltage with an external pul -down REXT maintain stable V follow: INPT voltage, while offering very low leakage current at the INPT pin. The current sourced by the low R impedance INPT pin is mirrored and sourced by the high V = EXT (V − SREF POS 1 0 . V ), V ≥ SREF 1 2 . V R + EXT 20kΩ impedance IOUT pin. R
BIAS CONTROL INTERFACE
V = EXT V , V ≤ 6 . 0 SREF POS SREF V R + EXT 20kΩ The voltage at the INPT pin, VINPT, is forced to be equal to the voltage applied to VSET by the mirror-biasing loop. The V where the 20 kΩ is the process-dependent internal resistor. SET voltage range extends down to ground, allowing the ADL5315
VPOS
to be used as a voltage-to-current converter with a single resistor from INPT to ground. This capability al ows dark current to be
ADL5315 VSET
minimized in PIN photodiode systems by maintaining a small
20k
Ω voltage bias. The VSET control also allows VINPT to be set approximately equal to the load voltage at IOUT. Balancing
SREF
the mirror voltages in this way provides inherently superior linearity over the widest current range independent of the
CSET 50
µ
A REXT 0.9V
supply voltage. Only leakage currents from the JFET op amp and ESD devices remain as significant sources of nonlinearity at very low currents. The voltage at VSET can also be used to 05964-029 shield the highly sensitive INPT pin and its board trace from Figure 20. Model of SREF Bias Source with External Pull-Down leakage currents, because the two pins operate at approximately the same potential. Care must be taken to provide a low noise VSET signal, since voltage noise at VSET also appears at INPT and is transformed by the input compensation network into current noise. Rev. A | Page 9 of 17 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BIAS CONTROL INTERFACE NOISE PERFORMANCE MIRROR RESPONSE TIME INPUT CURRENT LIMITING APPLICATIONS AVERAGE POWER MONITORING TRANSLINEAR LOG AMP INTERFACING EXTENDED OPERATING RANGE USING RLIM AS A SECONDARY MONITOR CHARACTERIZATION METHODS EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE