Datasheet ADP5075 (Analog Devices) - 3

Data Sheet ADP5075 SPECIFICATIONS
PVIN = AVIN = 2.85 V to 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.85 15 V PVIN, AVIN QUIESCENT CURRENT Operating Quiescent Current PVIN, AVIN (Total) IQ 1.8 4.0 mA No switching, EN = high, PVIN = AVIN = 5 V Shutdown Current ISHDN 5 10 µA No switching, EN = low, PVIN = AVIN = 5 V UVLO System UVLO Threshold AVIN Rising VUVLO_RISING 2.8 2.85 V Falling VUVLO_FALLING 2.5 2.55 V Hysteresis VHYS 0.25 V OSCILLATOR CIRCUIT Switching Frequency fSW 1.130 1.200 1.270 MHz SYNC/FREQ = low 2.240 2.400 2.560 MHz SYNC/FREQ = high (connect to VREG) SYNC/FREQ Input Input Clock Range fSYNC 1.000 2.600 MHz Input Clock Minimum On Pulse Width tSYNC_MIN_ON 100 ns Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns Input Clock High Logic VH (SYNC) 1.3 V Input Clock Low Logic VL (SYNC) 0.4 V PRECISION ENABLING (EN) High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to achieve ISHDN Pull-Down Resistance REN 1.48 MΩ INTERNAL REGULATOR VREG Output Voltage VREG 4.25 V INVERTING REGULATOR Reference Voltage VREF 1.60 V Accuracy −0.5 +0.5 % TJ = 25°C −1.5 +1.5 % TJ = −40°C to +125°C Feedback Voltage VREF − VFB 0.8 V Accuracy −0.5 +0.5 % TJ = 25°C −1.5 +1.5 % TJ = −40°C to +125°C Feedback Bias Current IFB 0.1 µA Overvoltage Protection Threshold VOV 0.74 V At the FB pin after soft start is complete Load Regulation ∆(VREF − VFB)/ 0.0004 %/mA ILOAD = 5 mA to 75 mA ILOAD Line Regulation ∆(VREF − VFB)/ 0.003 %/V VPVIN = 2.85 V to 14.5 V, ILOAD = 15 mA VPVIN EA Transconductance gM 270 300 330 µA/V Power FET On Resistance RDS (ON) 330 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) 39 V Current-Limit Threshold ILIM 800 880 960 mA Minimum On Time 60 ns Minimum Off Time 50 ns Rev. B | Page 3 of 19 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION PWM MODE PSM MODE UNDERVOLTAGE LOCKOUT (UVLO) OSCILLATOR AND SYNCHRONIZATION INTERNAL REGULATORS PRECISION ENABLING SOFT START SLEW RATE CONTROL CURRENT-LIMIT PROTECTION OVERVOLTAGE PROTECTION THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL COMPONENT SELECTION Feedback Resistors Output Capacitor Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection Loop Compensation COMMON APPLICATIONS LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE