Datasheet BC3602 (Holtek) - 7
| Hersteller | Holtek |
| Beschreibung | Sub-1GHz Low RX Current FSK/GFSK RF Transceiver |
| Seiten / Seite | 61 / 7 — BC3602. Strobe Command Only (CmdO). SFR Mapping and Bit Definition. … |
| Dateiformat / Größe | PDF / 1.3 Mb |
| Dokumentensprache | Englisch |
BC3602. Strobe Command Only (CmdO). SFR Mapping and Bit Definition. Common Area Control Register. Bit. Addr. Name
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BC3602
Reset RF register CMD RF RESET Reset TX FIFO pointer CMD TX FIFO RESET Reset RX FIFO register CMD RX FIFO RESET Set Register Bank CMD SET REG. BANK
Strobe Command Only (CmdO) SFR Mapping and Bit Definition Common Area Control Register
All control registers will be set to their initial value by power-on reset (POR). The software reset will set the control registers to their initial value except the FSYCK_EN, FSYCK_DIV[1:0], PWRON, GIO1S[2:0], GIO2S[2:0], PADDS[1:0], GIO3S[3:0], GIO4S[3:0], GIOPU[4:1], SPIPU, SDO_TEN bits in the RC1, IO1, IO2 and IO3 registers. These bits keep unchanged after software reset.
Bit Addr. Name 7 6 5 4 3 2 1 0
00h CFG1 — AGC_EN RXCON_ EN DIR_EN — — BANK[1:0] 01h RC1 PWRON FSYCK_RDY XCLK_RDY XCLK_EN FSYCK_DIV[1:0] FSYCK_ EN RST_LL 02h IRQ1 RXTO RXFFOW — — RXDETS[1:0] IRQCPOR IRQPOR 03h IRQ2 ARKTFIE ATRCTIE FIFOLTIE RXERRIE RXDETIE CALCMPIE RXCMPIE TXCMPIE 04h IRQ3 ARKTFIF ATRCTIF FIFOLTIF RXERRIF RXDETIF CALCMPIF RXCMPIF TXCMPIF 06h IO1 PADDS[1:0] GIO2S[2:0] GIO1S[2:0] 07h IO2 GIO4S[3:0] GIO3S[3:0] 08h IO3 SDO_TEN SPIPU — GIOPU[4:1] — 09h FIFO1 — — TXFFSA[5:0] 0Ah FIFO2 — — — RXPL2F_ EN FFINF_EN FFMG_EN FFMG[1:0] 0Bh PKT1 TXPMLEN[7:0] 0Ch PKT2 PID[1:0] TRAILER_ EN WHTFMT SYNCLEN[1:0] RXPMLEN[1:0] 0Dh PKT3 MCH_EN FEC_EN CRC_EN CRCFMT PLLEN_EN PLHAC_ EN PLHLEN PLH_EN 0Eh PKT4 WHT_EN WHTSD[6:0] 0Fh PKT5 TXDLEN[7:0] 10h PKT6 RXDLEN[7:0] 11h PKT7 RXPID[1:0] DLY_RXS[2:0] DLY_TXS[2:0] 12h PKT8 — PLHA[5:0] 13h PKT9 PLHEA[7:0] 14h MOD1 DTR[7:0] 15h MOD2 RXIFOS[11:8] DITHER[1:0] — DTR[8] 16h MOD3 RXIFOS[7:0] 17h DM1 — — MDIV[5:0] Rev. 1.00 7 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
Reset RF register CMD RF RESET Reset TX FIFO pointer CMD TX FIFO RESET Reset RX FIFO register CMD RX FIFO RESET Set Register Bank CMD SET REG. BANK
Strobe Command Only (CmdO) SFR Mapping and Bit Definition Common Area Control Register
All control registers will be set to their initial value by power-on reset (POR). The software reset will set the control registers to their initial value except the FSYCK_EN, FSYCK_DIV[1:0], PWRON, GIO1S[2:0], GIO2S[2:0], PADDS[1:0], GIO3S[3:0], GIO4S[3:0], GIOPU[4:1], SPIPU, SDO_TEN bits in the RC1, IO1, IO2 and IO3 registers. These bits keep unchanged after software reset.
Bit Addr. Name 7 6 5 4 3 2 1 0
00h CFG1 — AGC_EN RXCON_ EN DIR_EN — — BANK[1:0] 01h RC1 PWRON FSYCK_RDY XCLK_RDY XCLK_EN FSYCK_DIV[1:0] FSYCK_ EN RST_LL 02h IRQ1 RXTO RXFFOW — — RXDETS[1:0] IRQCPOR IRQPOR 03h IRQ2 ARKTFIE ATRCTIE FIFOLTIE RXERRIE RXDETIE CALCMPIE RXCMPIE TXCMPIE 04h IRQ3 ARKTFIF ATRCTIF FIFOLTIF RXERRIF RXDETIF CALCMPIF RXCMPIF TXCMPIF 06h IO1 PADDS[1:0] GIO2S[2:0] GIO1S[2:0] 07h IO2 GIO4S[3:0] GIO3S[3:0] 08h IO3 SDO_TEN SPIPU — GIOPU[4:1] — 09h FIFO1 — — TXFFSA[5:0] 0Ah FIFO2 — — — RXPL2F_ EN FFINF_EN FFMG_EN FFMG[1:0] 0Bh PKT1 TXPMLEN[7:0] 0Ch PKT2 PID[1:0] TRAILER_ EN WHTFMT SYNCLEN[1:0] RXPMLEN[1:0] 0Dh PKT3 MCH_EN FEC_EN CRC_EN CRCFMT PLLEN_EN PLHAC_ EN PLHLEN PLH_EN 0Eh PKT4 WHT_EN WHTSD[6:0] 0Fh PKT5 TXDLEN[7:0] 10h PKT6 RXDLEN[7:0] 11h PKT7 RXPID[1:0] DLY_RXS[2:0] DLY_TXS[2:0] 12h PKT8 — PLHA[5:0] 13h PKT9 PLHEA[7:0] 14h MOD1 DTR[7:0] 15h MOD2 RXIFOS[11:8] DITHER[1:0] — DTR[8] 16h MOD3 RXIFOS[7:0] 17h DM1 — — MDIV[5:0] Rev. 1.00 7 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions