Datasheet 5L2503 (IDT) - 9

5L2503 Datasheet
Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance
(TA = +25 °C)
Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Symbol Parameter Minimum Typical Maximum Units
CIN Input Capacitance (OE, SDA, SCL) 3 7 pF Pull-down Resistor OE 150 kΩ ROUT LVCMOS Output Driver Impedance (VDDOUTx = 1.8V) 17
Recommended Crystal Characteristics Table 16: Crystal Characteristics Parameter Minimum Typical Maximum Units
Mode of Oscillation Fundamental Frequency 8 48 MHz Frequency Tolerance -20 20 ppm Equivalent Series Resistance (ESR) 10 100 Ω Shunt Capacitance 2 7 pF Load Capacitance (CL) 6 8 10 pF Maximum Crystal Drive Level 100 μW
DC Electrical Characteristics Table 17: DC Electrical Characteristics Symbol Parameter Conditions Minimum Typical Maximum Units
VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 12MHz, 2.0 mA OUT3 = 26MHz, OUT2 off, no load. VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 12MHz, 3.5 mA Operation Supply OUT3 = 26MHz, OUT2 off, with load. IDD Current VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 26MHz, 1.8 mA OUT3 = 26MHz, OUT2 = 32kHz, no load. VDD = VDDO = VDD1_8 = 1.8V; OUT1 = 26MHz, 3.8 mA OUT3 = 26MHz, OUT2 = 32kHz, with load. Power Down PD asserted with V I DD1_8 and VDDO ON, I2C DDPD 390 μA Current programming, 32k running. Power Suspend V I DDOUT2 OFF and only VDDOUT1 and VDD1_8 DDSUSPEND 1.6 2.0 μA Current ON, I2C programming, 32k running. 1 Single CMOS driver active. 2 OUT1–3 current measured with 0.5 inches transmission line and no load. ©2017 Integrated Device Technology, Inc. 9 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History