Datasheet 5L2503 (IDT) - 5

5L2503 Datasheet
PPS – Proactive Power Saving Function
PPS Proactive Power Saving is an IDT patented unique design for the clock generator that proactively detects end device power-down state and then switches output clocks between normal operation clock frequency and low power mode 32kHz clock that only consumes < 5μA current. The system could save power when the device goes into power-down or sleep mode. The PPS function diagram is shown below.
Figure 3. PPS Function Block Diagram
PPS Control Power I2C Logic Down & Control Logic Low Power DCO XOUT Xtal Logic Oscillator Xtal XIN Oscil ator PLL MHz / kHz Switching
Figure 4. PPS Assertion/Deassertion Timing Chart
3rd cycle 2nd cycle 1st cycle PPS assertion MHz clock 32kHz clocks 2nd cycle 1st cycle PPS deassertion 32kHz clocks MHz clock
PPS Function Programming
▪ Refer to OE_pin_function_table to have proper PPS function selected for OE pin(s); note that register default is set to Output Enable (OE) function for OE pins. ©2017 Integrated Device Technology, Inc. 5 October 24, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN – Top View Pin Descriptions Table 1. Pin Descriptions Power Group Table 2. Power Group Output Source Selection Register Settings Table 3. OUT3 Source Table 4. OUT2 Source Table 5. OUT1 Source Table 6. DIV1 Source Device Features and Functions DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 7. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 8. OE1 Pin Function Table 9. SDA/SCL Function Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 10. Output Divider 1 Table 11. Output Dividers 2, 3, and 5 Table 12. Output Divider 4 Output Clock Test Conditions Absolute Maximum Ratings Table 13: Absolute Maximum Ratings Recommended Operating Conditions Table 14: Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 15: Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Recommended Crystal Characteristics Table 16: Crystal Characteristics DC Electrical Characteristics Table 17: DC Electrical Characteristics DC Electrical Characteristics for 1.8V LVCMOS Table 18: DC Electrical Characteristics for 1.8V LVCMOS AC Electrical Characteristics Table 19. AC Electrical Characteristics I2C Bus Characteristics Table 20. I2C Bus DC Characteristics Table 21. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 22: Spread Spectrum Generation Specifications General I2C Serial Interface Information Package Drawings Figure 5. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 1 Figure 6. NVG12, 2.5 × 2.5 mm 12-DFN Package Drawing – Page 2 Marking Diagram Ordering Information Revision History