Datasheet STNRGPF12 (STMicroelectronics) - 10

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STNRGPF12 block diagram STNRGPF12 3 STNRGPF12 block diagram
The block diagram of the STNRGPF12 device is shown in Figure 4.
Figure 4. STNRGPF12 block diagram ^dEZ'W&ϭϮ
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3.1 Voltage and current loops
The STNRGPF12 implements a mixed signal average current control. The task of the digital voltage loop is to regulate the output voltage of the PFC. Vin and Iout measurements are used to implement Input/Output Feed-Forward (I/O FFD), so load steps or input voltage variations are quickly compensated by acting on digital PI output calculations. This function allows to keep the output voltage to the setpoint value and as constant as possible (see Figure 5). 10/47 DS12895 Rev 1 Document Outline Table 1. Device summary List of tables List of figures Documentation 1 General description 1.1 Inrush current limiter function description 1.1.1 Inrush current limiter function with resistive element Figure 1. Inrush current limiter with resistor in series to output capacitor 1.1.2 Inrush current limiter function with controlled bridge Figure 2. Inrush current limiter with controlled rectifier bridge 2 STNRGPF12 control architecture Figure 3. STNRGPF12 control scheme 3 STNRGPF12 block diagram Figure 4. STNRGPF12 block diagram 3.1 Voltage and current loops Figure 5. Voltage loop and current reference 3.2 Measurements section 3.2.1 AC input voltage measurement Figure 6. Vin, measurement 3.2.2 Ambient temperature measurements Figure 7. Temperature measurement 3.2.3 Output current measurement 3.2.4 Output voltage sensing Figure 8. Iout and Vout measurement 3.2.5 Channel current measurement Figure 9. Channel current measurement 3.3 Analog comparators section Figure 10. Analog comparators section 3.4 Driving & Interleaving Figure 11. Driving & interleaving 3.5 Programming section Figure 12. Programming section 3.6 Status indicator Figure 13. Status indicator 3.7 Startup & inrush current limiter function Figure 14. Start-up sequence 3.7.1 Inrush current limiter function Figure 15. Inrush current limiter function with limiter resistor and bypass relay Figure 16. Digital inrush current limiter function with a semi-controlled input bridge Figure 17. Digital inrush current limiter function: sequence of driving of the SCR 3.7.2 PFC soft power-ON Figure 18. Running mode or burst mode 3.8 Fan control Figure 19. Fan Control function 4 Pinout and pin description 4.1 Pinout Figure 20. STNRGPF12 - TSSOP38 pinout 4.2 Pin description Table 2. Pin description (continued) Table 3. Legend of the pins 4.3 Input/output specification 5 Electrical characteristics 5.1 Parameter conditions 5.1.1 Minimum and maximum values 5.1.2 Typical values 5.1.3 Typical curves 5.1.4 Typical current consumption Figure 21. Supply current measurement conditions 5.1.5 Loading capacitors Figure 22. Pin loading conditions 5.1.6 Pin output voltage Figure 23. Pin input voltage 5.2 Absolute maximum ratings Table 4. Voltage characteristics Table 5. Current characteristics Table 6. Thermal characteristics 5.3 Operating conditions Table 7. General operating conditions Table 8. Operating conditions at power-up/power-down 5.3.1 VOUT external capacitor Figure 24. External capacitor CVOUT 5.3.2 Supply current characteristics Table 9. Supply current characteristics 5.3.3 Memory characteristics Table 10. Flash program memory/data E2PROM 5.3.4 Input/output specifications 5.3.5 I/O port pin characteristics Table 11. Voltage DC characteristics Table 12. Current DC characteristics 5.3.6 Typical output level curves Figure 25. VOH normal pin Figure 26. VOL normal pin Figure 27. VOH fast I/Os pins Figure 28. VOL fast I/Os pins Figure 29. VOH CLOCK pin Figure 30. VOL CLOCK pin 5.3.7 Reset pin characteristics Table 13. NRST pin characteristics 5.4 Analog input characteristics 5.4.1 Measurement section Table 14. Measurement pin characteristics 5.4.2 Analog section Table 15. Analog comparator characteristics 5.5 EMC characteristics 5.5.1 Electrostatic discharge (ESD) Table 16. ESD absolute maximum ratings 5.5.2 Static latch-up Table 17. Electrical sensitivity 6 Thermal data Table 18. Package thermal characteristics 7 Package information 7.1 TSSOP38 package information Figure 31. TSSOP38 package outline Table 19. TSSOP38 package mechanical data 8 STNRGPF12 development tools 9 Ordering information Table 20. Ordering information 10 Revision history Table 21. Document history