Datasheet RX65N, RX651 Groups (Renesas) - 7
| Hersteller | Renesas |
| Beschreibung | 120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory |
| Seiten / Seite | 246 / 7 — Table 1.1. Outline of Specifications (6/10). Classification. … |
| Dateiformat / Größe | PDF / 2.8 Mb |
| Dokumentensprache | Englisch |
Table 1.1. Outline of Specifications (6/10). Classification. Module/Function. Description
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link to page 11 link to page 11 RX65N Group, RX651 Group 1. Overview
Table 1.1 Outline of Specifications (6/10) Classification Module/Function Description
Timers 8-bit timers (TMRb) (8 bits × 2 channels) × 2 units Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Generation of triggers for A/D converter conversion Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12 Event linking by the ELC Compare match timer (16 bits × 2 channels) × 2 units (CMT) Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Event linking by the ELC Compare match timer W (32 bits × 1 channel) × 2 units (CMTW) Compare-match, input-capture input, and output-comparison output are available. Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. Event linking by the ELC Realtime clock (RTCd)*4 Clock sources: Main clock, sub clock Selection of the 32-bit binary count in time count/second unit possible Clock and calendar functions Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Battery backup operation Time-capture facility for three values Event linking by the ELC Watchdog timer (WDTA) 14 bits × 1 channel Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128, PCLKB/512, PCLKB/2048, PCLKB/8192) Independent watchdog 14 bits × 1 channel timer (IWDTa) Counter-input clock: IWDT-dedicated on-chip oscillator Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 Window function: The positions where the window starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled). Event linking by the ELC Communication Ethernet controller Input and output of Ethernet/IEEE 802.3 frames function (ETHERC) Transfer at 10 or 100 Mbps Full- and half-duplex modes MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as defined in IEEE 802.3u Detection of Magic PacketsTM*1 or output of a “wake-on-LAN” signal (WOL) Compliance with flow control as defined in IEEE 802.3x standards DMA controller for Alleviation of CPU load by the descriptor control method Ethernet controller Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes (EDMACa) USB 2.0 FS host/ Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS function module (USBb) One port Compliance with the USB 2.0 specification Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only) Both self-powered mode and bus-powered mode are supported OTG (On the Go) operation is possible (low-speed is not supported) Incorporates 2 Kbytes of RAM as a transfer buffer External pull-up and pull-down resistors are not required R01DS0276EJ0230 Rev.2.30 Page 7 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice
Table 1.1 Outline of Specifications (6/10) Classification Module/Function Description
Timers 8-bit timers (TMRb) (8 bits × 2 channels) × 2 units Select from among seven internal clock signals (PCLKB/1, PCLKB/2, PCLKB/8, PCLKB/32, PCLKB/64, PCLKB/1024, PCLKB/8192) and one external clock signal Capable of output of pulse trains with desired duty cycles or of PWM signals The 2 channels of each unit can be cascaded to create a 16-bit timer Generation of triggers for A/D converter conversion Capable of generating baud-rate clocks for SCI5, SCI6, and SCI12 Event linking by the ELC Compare match timer (16 bits × 2 channels) × 2 units (CMT) Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Event linking by the ELC Compare match timer W (32 bits × 1 channel) × 2 units (CMTW) Compare-match, input-capture input, and output-comparison output are available. Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128, PCLKB/512) Interrupt requests can be output in response to compare-match, input-capture, and output-comparison events. Event linking by the ELC Realtime clock (RTCd)*4 Clock sources: Main clock, sub clock Selection of the 32-bit binary count in time count/second unit possible Clock and calendar functions Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt Battery backup operation Time-capture facility for three values Event linking by the ELC Watchdog timer (WDTA) 14 bits × 1 channel Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128, PCLKB/512, PCLKB/2048, PCLKB/8192) Independent watchdog 14 bits × 1 channel timer (IWDTa) Counter-input clock: IWDT-dedicated on-chip oscillator Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated clock/128, dedicated clock/256 Window function: The positions where the window starts and ends are specifiable (the window defines the timing with which refreshing is enabled and disabled). Event linking by the ELC Communication Ethernet controller Input and output of Ethernet/IEEE 802.3 frames function (ETHERC) Transfer at 10 or 100 Mbps Full- and half-duplex modes MII (Media Independent Interface) or RMII (Reduced Media Independent Interface) as defined in IEEE 802.3u Detection of Magic PacketsTM*1 or output of a “wake-on-LAN” signal (WOL) Compliance with flow control as defined in IEEE 802.3x standards DMA controller for Alleviation of CPU load by the descriptor control method Ethernet controller Transmission FIFO: 2 Kbytes; Reception FIFO: 2 Kbytes (EDMACa) USB 2.0 FS host/ Includes a UDC (USB Device Controller) and transceiver for USB 2.0 FS function module (USBb) One port Compliance with the USB 2.0 specification Transfer rate: Full speed (12 Mbps), low speed (1.5 Mbps) (host only) Both self-powered mode and bus-powered mode are supported OTG (On the Go) operation is possible (low-speed is not supported) Incorporates 2 Kbytes of RAM as a transfer buffer External pull-up and pull-down resistors are not required R01DS0276EJ0230 Rev.2.30 Page 7 of 246 Jun 20, 2019 Document Outline Features 1. Overview 1.1 Outline of Specifications 1.2 List of Products 1.3 Block Diagram 1.4 Pin Functions 1.5 Pin Assignments 2. CPU 2.1 General-Purpose Registers (R0 to R15) 2.2 Control Registers 2.3 Accumulator 3. Address Space 3.1 Address Space 3.2 External Address Space 4. I/O Registers 4.1 I/O Register Addresses (Address Order) 5. Electrical Characteristics 5.1 Absolute Maximum Ratings 5.2 DC Characteristics 5.3 AC Characteristics 5.3.1 Reset Timing 5.3.2 Clock Timing 5.3.3 Timing of Recovery from Low Power Consumption Modes 5.3.4 Control Signal Timing 5.3.5 Bus Timing 5.3.6 EXDMAC Timing 5.3.7 Timing of On-Chip Peripheral Modules 5.4 USB Characteristics 5.5 A/D Conversion Characteristics 5.6 D/A Conversion Characteristics 5.7 Temperature Sensor Characteristics 5.8 Power-on Reset Circuit and Voltage Detection Circuit Characteristics 5.9 Oscillation Stop Detection Timing 5.10 Battery Backup Function Characteristics 5.11 Flash Memory Characteristics 5.12 Boundary Scan Appendix 1. Package Dimensions REVISION HISTORY General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products Notice