Datasheet MAX98390 (Maxim) - 7

link to page 34 link to page 37 link to page 39 link to page 41 link to page 42 link to page 44 link to page 44 link to page 44 link to page 45 link to page 45 link to page 46 link to page 50 link to page 50 link to page 51 link to page 52 link to page 54 link to page 54 link to page 54 link to page 56 link to page 58 link to page 61 link to page 63 link to page 64 link to page 65 link to page 66 link to page 67 link to page 67 link to page 67 link to page 67 link to page 68 link to page 68 link to page 69 link to page 69 link to page 69 link to page 70 link to page 71 link to page 73 link to page 73 link to page 73 link to page 73 link to page 74 link to page 74 link to page 74 link to page 74 link to page 75 link to page 75 MAX98390 Boosted Class-D Amplifier with Integrated Dynamic Speaker Management LIST OF FIGURES Figure 1. DSM Path . 34 Figure 2. Interrupt Logic . 37 Figure 3. Boost Converter Block Diagram . 39 Figure 4. Boost Envelope Tracker . 41 Figure 5. Boost Bypass . 42 Figure 6. Clock Monitor LRCLK Rate Error Example with CMON_ERRTOL = 0x1 . 44 Figure 7. Clock Monitor Framing Error Example in TDM Mode with PCM_BSEL = 0x6 (128 BCLKs per LRCLK) and CMON_BSELTOL = 0x0 . 44 Figure 8. Data Stuck Error Example . 45 Figure 9. Data Magnitude Error Example . 45 Figure 10. Watchdog Timer Period . 46 Figure 11. I2S Mode . 50 Figure 12. Left-Justified Modes . 51 Figure 13. TDM Modes . 52 Figure 14. PCM Interface Timing/Master Mode—LRCLK, BCLK, DIN Timing Diagram . 54 Figure 15. PCM Interface Timing/Slave Mode—LRCLK, BCLK, DIN Timing Diagram . 54 Figure 16. PCM Interface Timing/DOUT Timing Diagram . 54 Figure 17. Amplifier Path . 56 Figure 18. Output Sensing When Using Ferrite Beads . 58 Figure 19. BDE Block Diagram . 61 Figure 20. BDE Levels . 63 Figure 21. Limiter Profile Example with -6dBFS Knee Point . 64 Figure 22. Gain Reduction Profile Example with -6dB Setting . 65 Figure 23. Clipper Examples with Level Change from -12dBFS to -6dBFS . 66 Figure 24. Acceptable VVBAT Sag . 67 Figure 25. Unacceptable VVBAT Sag . 67 Figure 26. Reduced Boost ILIM for Reduced VVBAT Sag . 68 Figure 27. ICC Transmit Frame Structure (16-bit Left-Justified) . 69 Figure 28. ICC Transmit Frame Structure (24-bit or 32-bit Left-Justified) . 69 Figure 29. PCM Interface Timing/Interchip Communication—ICC Timing Diagram . 69 Figure 30. ICC Grouping Example . 70 Figure 31. RESET Timing Diagram . 71 Figure 32. I2C Interface Timing Diagram . 73 Figure 33. I2C START, STOP, and REPEATED START Conditions . 73 Figure 34. I2C Acknowledge . 74 Figure 35. I2C Writing One Byte of Data to the Slave . 74 Figure 36. I2C Writing n-Bytes of Data to the Slave . 75 www.maximintegrated.com Maxim Integrated | 7 Document Outline General Description Applications Benefits and Features Simplified Block Diagram Absolute Maximum Ratings Package Information 36 WLP Electrical Characteristics Typical Operating Characteristics Pin Configuration 36 WLP Pin Description Functional Diagram MAX98390 Detailed Description Integrated Dynamic Speaker Management (DSM) DSM Sound Studio Thermal and Excursion Protection Low-Frequency Extension Perceptual Power Reduction (PPR) Stereo Bass Management Debuzzer Dynamic Range Compression Equalizer Reading and Writing DSM Registers Interrupts IRQ Pin Configuration Interrupt Sources Boost Converter Soft-Start Boost Output Undervoltage Lockout Boost Overvoltage Protection Programmable Boost Input Current Limit Boost-Clock Phase Boost-Skip Mode Supplying PVDD Externally Boost Envelope Tracker Automatic Boost Bypass Delay for Envelope Tracker and Automatic Boost Bypass Host Fault Handling Clock Monitor BCLK and LRCLK Rate Detection PCM Framing Error Detection Input Data Monitor Watchdog Timer Software Mode Hardware Mode PCM Interface PCM Master/Slave Modes and MCLK Interface Formats—All Modes PCM Clock Ratio Configuration I2S and Left-Justified Modes TDM Modes Invalid TDM Configurations PCM Data Path Configuration PCM Data Input PCM Data Output PCM Interface Timing Logic Output Pin Drive Strength Control Tone Generator Thermal Warning and Shutdown Minimum Valid Setup Thermal Thresholds Amplifier Path Controls Path Routing Control Power Gating and Auto Muting PCM Dither DAC Inversion DC Blocking Filter Digital Volume Control Dynamic Range Extension (DRE) DSP Monitor Class-D Amplifier Output Short-Circuit Detection Spread-Spectrum Modulation Output Sensing When Using Ferrite Beads Ultra-Low EMI Filterless Output Stage FET Scaling Current and Voltage Sense I/V Sense Channel Sharing Measurement ADC Brownout-Detection Engine (BDE) BDE Gain, Limit, and Clip Mirroring BDE Enable Control VBAT Measurement Brownout Controller Brownout Interrupts Limiter Gain Reduction Level 4 Mute Clipper Boost Input Current Limit Using Brownout Boost Input Current Limit to Avoid System Brownouts Interchip Communication ICC Operation and Data Format Multiamplifier Grouping Shutdown Modes Software Shutdown Software Reset Hardware Shutdown I2C Serial Interface Slave Address Bit Transfer START and STOP Conditions Early STOP Conditions Acknowledge Write Data Format Read Data Format I2C Register Map Control Bit Types and Write-Access Restrictions Register Map Register Map Register Details SOFTWARE RESET (0x2000) INTERRUPT RAW 1 (0x2002) INTERRUPT RAW 2 (0x2003) INTERRUPT RAW 3 (0x2004) INTERRUPT STATE 1 (0x2005) INTERRUPT STATE 2 (0x2006) INTERRUPT STATE 3 (0x2007) INTERRUPT FLAG 1 (0x2008) INTERRUPT FLAG 2 (0x2009) INTERRUPT FLAG 3 (0x200A) INTERRUPT ENABLE 1 (0x200B) INTERRUPT ENABLE 2 (0x200C) INTERRUPT ENABLE 3 (0x200D) INTERRUPT FLAG CLEAR 1 (0x200E) INTERRUPT FLAG CLEAR 2 (0x200F) INTERRUPT FLAG CLEAR 3 (0x2010) IRQ CONTROL (0x2011) CLOCK MONITOR CONTROL (0x2012) DATA MONITOR CONTROL (0x2014) WATCHDOG CONTROL (0x2015) WATCHDOG SW RESET (0x2016) MEAS ADC THERMAL WARNING THRESHHOLD (0x2017) MEAS ADC THERMAL SHUTDOWN THRESHHOLD (0x2018) MEAS ADC THERMAL HYSTERESIS (0x2019) PIN CONFIG (0x201A) PCM RX ENABLES A (0x201B) PCM RX ENABLES B (0x201C) PCM TX ENABLES A (0x201D) PCM TX ENABLES B (0x201E) PCM TX HIZ CONTROL A (0x201F) PCM TX HIZ CONTROL B (0x2020) PCM CHANNEL SOURCES 1 (0x2021) PCM CHANNEL SOURCES 2 (0x2022) PCM CHANNEL SOURCES 3 (0x2023) PCM MODE CONFIG (0x2024) PCM MASTER MODE (0x2025) PCM CLOCK SETUP (0x2026) PCM SAMPLE RATE SETUP 1 (0x2027) ICC RX ENABLES A (0x202C) ICC RX ENABLES B (0x202D) ICC TX ENABLES A (0x202E) ICC TX ENABLES B (0x202F) ICC HIZ MANUAL MODE (0x2030) ICC TX HIZ ENABLES A (0x2031) ICC TX HIZ ENABLES B (0x2032) ICC LINK ENABLES (0x2033) AMP DSP CONFIG (0x2039) AMP ENABLES (0x203A) TONE GENERATOR AND DC CONFIG (0x203B) SPEAKER SOURCE SELECT (0x203C) SSM CONFIGURATION (0x203E) MEASUREMENT ENABLES (0x203F) MEASUREMENT DSP CONFIG (0x2040) BOOST CONTROL 0 (0x2041) BOOST CONTROL 3 (0x2042) BOOST CONTROL 1 (0x2043) MEAS ADC CONFIG (0x2044) MEAS ADC BASE DIVIDE MSBYTE (0x2045) MEAS ADC BASE DIVIDE LSBYTE (0x2046) MEAS ADC CHAN 0 DIVIDE (0x2047) MEAS ADC CHAN 1 DIVIDE (0x2048) MEAS ADC CHAN 2 DIVIDE (0x2049) MEAS ADC CHAN 0 FILT CONFIG (0x204A) MEAS ADC CHAN 1 FILT CONFIG (0x204B) MEAS ADC CHAN 2 FILT CONFIG (0x204C) MEAS ADC CHAN 0 READBACK (0x204D) MEAS ADC CHAN 1 READBACK (0x204E) MEAS ADC CHAN 2 READBACK (0x204F) DSP POWER GATING CONTROL (0x2050) DSP POWER GATING STATUS (0x2051) VBAT LOWEST STATUS (0x2052) PVDD LOWEST STATUS (0x2053) BROWNOUT STATUS (0x2054) BROWNOUT ENABLES (0x2055) BROWNOUT LEVEL INFINITE HOLD (0x2056) BROWNOUT LEVEL INFINITE HOLD CLEAR (0x2057) BROWNOUT LEVEL HOLD (0x2058) BROWNOUT LEVEL 1 THRESHOLD (0x2059) BROWNOUT LEVEL 2 THRESHOLD (0x205A) BROWNOUT LEVEL 3 THRESHOLD (0x205B) BROWNOUT LEVEL 4 THRESHOLD (0x205C) BROWNOUT THRESHOLD HYSTERYSIS (0x205D) BROWNOUT AMP LIMITER ATTACK RELEASE (0x205E) BROWNOUT AMP GAIN ATTACK RELEASE (0x205F) BROWNOUT AMP1 CLIP MODE (0x2060) BROWNOUT LEVEL 1 CURRENT LIMIT (0x2061) BROWNOUT LEVEL 1 AMP 1 CONTROL 1 (0x2062) BROWNOUT LEVEL 1 AMP 1 CONTROL 2 (0x2063) BROWNOUT LEVEL 1 AMP 1 CONTROL 3 (0x2064) BROWNOUT LEVEL 2 CURRENT LIMIT (0x2065) BROWNOUT LEVEL 2 AMP 1 CONTROL 1 (0x2066) BROWNOUT LEVEL 2 AMP 1 CONTROL 2 (0x2067) BROWNOUT LEVEL 2 AMP 1 CONTROL 3 (0x2068) BROWNOUT LEVEL 3 CURRENT LIMIT (0x2069) BROWNOUT LEVEL 3 AMP 1 CONTROL 1 (0x206A) BROWNOUT LEVEL 3 AMP 1 CONTROL 2 (0x206B) BROWNOUT LEVEL 3 AMP 1 CONTROL 3 (0x206C) BROWNOUT LEVEL 4 CURRENT LIMIT (0x206D) BROWNOUT LEVEL 4 AMP 1 CONTROL 1 (0x206E) BROWNOUT LEVEL 4 AMP 1 CONTROL 2 (0x206F) BROWNOUT LEVEL 4 AMP 1 CONTROL 3 (0x2070) BROWNOUT LOWEST STATUS (0x2071) BROWNOUT ILIM HOLD (0x2072) BROWNOUT LIM HOLD (0x2073) BROWNOUT CLIP HOLD (0x2074) BROWNOUT GAIN HOLD (0x2075) ENV TRACKER VOUT HEADROOM (0x2076) ENV TRACKER BOOST VOUT DELAY (0x2077) ENV TRACKER RELEASE RATE (0x2078) ENV TRACKER HOLD RATE (0x2079) ENV TRACKER CONTROL (0x207A) ENV TRACKER BOOST VOUT READBACK (0x207B) BOOST BYPASS 1 (0x207C) BOOST BYPASS 2 (0x207D) BOOST BYPASS 3 (0x207E) FET SCALING 1 (0x207F) FET SCALING 2 (0x2080) FET SCALING 3 (0x2081) FET SCALING 4 (0x2082) ADVANCED SETTINGS (0x2084) DSM_EQ_BQ1_B0_BYTE0 (0x2129) DSM_EQ_BQ1_B0_BYTE1 (0x212A) DSM_EQ_BQ1_B0_BYTE2 (0x212B) DSM_EQ_BQ1_B1_BYTE0 (0x212D) DSM_EQ_BQ1_B1_BYTE1 (0x212E) DSM_EQ_BQ1_B1_BYTE2 (0x212F) DSM_EQ_BQ1_B2_BYTE0 (0x2131) DSM_EQ_BQ1_B2_BYTE1 (0x2132) DSM_EQ_BQ1_B2_BYTE2 (0x2133) DSM_EQ_BQ1_A1_BYTE0 (0x2135) DSM_EQ_BQ1_A1_BYTE1 (0x2136) DSM_EQ_BQ1_A1_BYTE2 (0x2137) DSM_EQ_BQ1_A2_BYTE0 (0x2139) DSM_EQ_BQ1_A2_BYTE1 (0x213A) DSM_EQ_BQ1_A2_BYTE2 (0x213B) DSM_EQ_BQ2_B0_BYTE0 (0x213D) DSM_EQ_BQ2_B0_BYTE1 (0x213E) DSM_EQ_BQ2_B0_BYTE2 (0x213F) DSM_EQ_BQ2_B1_BYTE0 (0x2141) DSM_EQ_BQ2_B1_BYTE1 (0x2142) DSM_EQ_BQ2_B1_BYTE2 (0x2143) DSM_EQ_BQ2_B2_BYTE0 (0x2145) DSM_EQ_BQ2_B2_BYTE1 (0x2146) DSM_EQ_BQ2_B2_BYTE2 (0x2147) DSM_EQ_BQ2_A1_BYTE0 (0x2149) DSM_EQ_BQ2_A1_BYTE1 (0x214A) DSM_EQ_BQ2_A1_BYTE2 (0x214B) DSM_EQ_BQ2_A2_BYTE0 (0x214D) DSM_EQ_BQ2_A2_BYTE1 (0x214E) DSM_EQ_BQ2_A2_BYTE2 (0x214F) DSM_EQ_BQ3_B0_BYTE0 (0x2151) DSM_EQ_BQ3_B0_BYTE1 (0x2152) DSM_EQ_BQ3_B0_BYTE2 (0x2153) DSM_EQ_BQ3_B1_BYTE0 (0x2155) DSM_EQ_BQ3_B1_BYTE1 (0x2156) DSM_EQ_BQ3_B1_BYTE2 (0x2157) DSM_EQ_BQ3_B2_BYTE0 (0x2159) DSM_EQ_BQ3_B2_BYTE1 (0x215A) DSM_EQ_BQ3_B2_BYTE2 (0x215B) DSM_EQ_BQ3_A1_BYTE0 (0x215D) DSM_EQ_BQ3_A1_BYTE1 (0x215E) DSM_EQ_BQ3_A1_BYTE2 (0x215F) DSM_EQ_BQ3_A2_BYTE0 (0x2161) DSM_EQ_BQ3_A2_BYTE1 (0x2162) DSM_EQ_BQ3_A2_BYTE2 (0x2163) DSM_EQ_BQ4_B0_BYTE0 (0x2165) DSM_EQ_BQ4_B0_BYTE1 (0x2166) DSM_EQ_BQ4_B0_BYTE2 (0x2167) DSM_EQ_BQ4_B1_BYTE0 (0x2169) DSM_EQ_BQ4_B1_BYTE1 (0x216A) DSM_EQ_BQ4_B1_BYTE2 (0x216B) DSM_EQ_BQ4_B2_BYTE0 (0x216D) DSM_EQ_BQ4_B2_BYTE1 (0x216E) DSM_EQ_BQ4_B2_BYTE2 (0x216F) DSM_EQ_BQ4_A1_BYTE0 (0x2171) DSM_EQ_BQ4_A1_BYTE1 (0x2172) DSM_EQ_BQ4_A1_BYTE2 (0x2173) DSM_EQ_BQ4_A2_BYTE0 (0x2175) DSM_EQ_BQ4_A2_BYTE1 (0x2176) DSM_EQ_BQ4_A2_BYTE2 (0x2177) DSM_EQ_BQ5_B0_BYTE0 (0x2179) DSM_EQ_BQ5_B0_BYTE1 (0x217A) DSM_EQ_BQ5_B0_BYTE2 (0x217B) DSM_EQ_BQ5_B1_BYTE0 (0x217D) DSM_EQ_BQ5_B1_BYTE1 (0x217E) DSM_EQ_BQ5_B1_BYTE2 (0x217F) DSM_EQ_BQ5_B2_BYTE0 (0x2181) DSM_EQ_BQ5_B2_BYTE1 (0x2182) DSM_EQ_BQ5_B2_BYTE2 (0x2183) DSM_EQ_BQ5_A1_BYTE0 (0x2185) DSM_EQ_BQ5_A1_BYTE1 (0x2186) DSM_EQ_BQ5_A1_BYTE2 (0x2187) DSM_EQ_BQ5_A2_BYTE0 (0x2189) DSM_EQ_BQ5_A2_BYTE1 (0x218A) DSM_EQ_BQ5_A2_BYTE2 (0x218B) DSM_EQ_BQ6_B0_BYTE0 (0x218D) DSM_EQ_BQ6_B0_BYTE1 (0x218E) DSM_EQ_BQ6_B0_BYTE2 (0x218F) DSM_EQ_BQ6_B1_BYTE0 (0x2191) DSM_EQ_BQ6_B1_BYTE1 (0x2192) DSM_EQ_BQ6_B1_BYTE2 (0x2193) DSM_EQ_BQ6_B2_BYTE0 (0x2195) DSM_EQ_BQ6_B2_BYTE1 (0x2196) DSM_EQ_BQ6_B2_BYTE2 (0x2197) DSM_EQ_BQ6_A1_BYTE0 (0x2199) DSM_EQ_BQ6_A1_BYTE1 (0x219A) DSM_EQ_BQ6_A1_BYTE2 (0x219B) DSM_EQ_BQ6_A2_BYTE0 (0x219D) DSM_EQ_BQ6_A2_BYTE1 (0x219E) DSM_EQ_BQ6_A2_BYTE2 (0x219F) DSM_EQ_BQ7_B0_BYTE0 (0x21A1) DSM_EQ_BQ7_B0_BYTE1 (0x21A2) DSM_EQ_BQ7_B0_BYTE2 (0x21A3) DSM_EQ_BQ7_B1_BYTE0 (0x21A5) DSM_EQ_BQ7_B1_BYTE1 (0x21A6) DSM_EQ_BQ7_B1_BYTE2 (0x21A7) DSM_EQ_BQ7_B2_BYTE0 (0x21A9) DSM_EQ_BQ7_B2_BYTE1 (0x21AA) DSM_EQ_BQ7_B2_BYTE2 (0x21AB) DSM_EQ_BQ7_A1_BYTE0 (0x21AD) DSM_EQ_BQ7_A1_BYTE1 (0x21AE) DSM_EQ_BQ7_A1_BYTE2 (0x21AF) DSM_EQ_BQ7_A2_BYTE0 (0x21B1) DSM_EQ_BQ7_A2_BYTE1 (0x21B2) DSM_EQ_BQ7_A2_BYTE2 (0x21B3) DSM_EQ_BQ8_B0_BYTE0 (0x21B5) DSM_EQ_BQ8_B0_BYTE1 (0x21B6) DSM_EQ_BQ8_B0_BYTE2 (0x21B7) DSM_EQ_BQ8_B1_BYTE0 (0x21B9) DSM_EQ_BQ8_B1_BYTE1 (0x21BA) DSM_EQ_BQ8_B1_BYTE2 (0x21BB) DSM_EQ_BQ8_B2_BYTE0 (0x21BD) DSM_EQ_BQ8_B2_BYTE1 (0x21BE) DSM_EQ_BQ8_B2_BYTE2 (0x21BF) DSM_EQ_BQ8_A1_BYTE0 (0x21C1) DSM_EQ_BQ8_A1_BYTE1 (0x21C2) DSM_EQ_BQ8_A1_BYTE2 (0x21C3) DSM_EQ_BQ8_A2_BYTE0 (0x21C5) DSM_EQ_BQ8_A2_BYTE1 (0x21C6) DSM_EQ_BQ8_A2_BYTE2 (0x21C7) DSMIG WB DRC RELEASE TIME 1 (0x2380) DSMIG WB DRC RELEASE TIME 2 (0x2381) DSMIG WB DRC ATTACK TIME 1 (0x2382) DSMIG WB DRC ATTACK TIME 2 (0x2383) DSMIG WB DRC COMPRESSION RATIO (0x2384) DSMIG WB DRC COMPRESSION THRESHOLD (0x2385) DSMIG WB DRC MAKEUPGAIN (0x2386) DSMIG WB DRC NOISE GATE THRESHOLD (0x2387) DSMIG WBDRC HPF ENABLE (0x2388) DSMIG PPR THRESHOLD (0x238B) DSM TPROT THRESHOLD BYTE 0 (0x238E) DSM TPROT THRESHOLD BYTE 1 (0x238F) DSM TPROT ROOM TEMPERATURE BYTE0 (0x2390) DSM TPROT ROOM TEMPERATURE BYTE 1 (0x2391) DSM TPROT RECIP RDC ROOM BYTE0 (0x2392) DSM TPROT RECIP RDC ROOM BYTE1 (0x2393) DSM TPROT RECIP RDC ROOM BYTE2 (0x2394) DSM TPROT RECIP TCONST BYTE0 (0x2395) DSM TPROT RECIP TCONST BYTE1 (0x2396) DSM TPROT RECIP TCONST BYTE2 (0x2397) DSM TPROT ATTENUATION SETTINGS (0x2398) DSM TPROT PG TEMP THRESH BYTE0 (0x239A) DSM TPROT PG TEMP THRESH BYTE1 (0x239B) THERMAL RESISTANCE RD BACK BYTE1 (0x239C) THERMAL RESISTANCE RD BACK BYTE0 (0x239D) DSMIG EXCURSION PROTECTION RELEASE TIME BYTE 0 (0x23A4) DSMIG EXCURSION PROTECTION RELEASE TIME BYTE 1 (0x23A5) DSMIG EXCURSION PROTECTION THRESHOLD (0x23A6) DSMIG EXCURSION PROTECTION DEL BUFFER (0x23A7) DSMIG DEBUZZER THRESHOLD (0x23B5) DSM VOL ENA (0x23B9) DSM_VOL_CTRL (0x23BA) DSMIG ENABLES (0x23E0) DSP GLOBAL ENABLE (0x23E1) DSM_THERMAL_GAIN (0x23F0) DSM_PPR_GAIN (0x23F1) DSM_DBZ_GAIN (0x23F2) DSM_WBDRC_GAIN (0x23F3) GLOBAL ENABLE (0x23FF) REV ID (0x24FF) Applications Information Boost Converter Component Selection Battery Input Capacitor Selection Boost Inductor Selection (L1) Power Amplifier Supply Bypass Capacitors (CPVDD) Boost Converter Settings Startup Sequence Shutdown Sequence Recommended External Components Typical Application Circuit MAX98390 Ordering Information Revision History