Datasheet InnoSwitch3-MX (Power Integrations) - 7

InnoSwitch3-MX Maximum Secondary Inhibit Period
In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to Secondary requests to initiate primary switching are inhibited to be open or the SYNCHRONOUS RECTIFIER DRIVE pin is tied to maintain operation below maximum frequency and ensure minimum ground at start-up, the secondary control er will stop requesting off-time. Besides these constraints, secondary-cycle requests are pulses from the primary to initiate auto-restart. also inhibited during the “ON” time cycle of the primary switch (time between the cycle request and detection of FORWARD pin falling It is possible to use a normal diode instead of an SR MOSFET. In that edge). The maximum time-out in the event that a FORWARD pin case, a 220 pF capacitor should be connected to the SR pin. falling edge is not detected after a cycle requested is ~30 µs.
Intelligent Quasi-Resonant Mode Switching SR Disable Protection
In order to improve conversion efficiency and reduce switching In each cycle SR is only engaged if a set cycle was requested by the losses, the InnoSwitch3-MX features a means to force switching when secondary control er and the negative edge is detected on the the voltage across the primary switch is near its minimum voltage FORWARD pin. when the converter operates in discontinuous conduction mode (DCM). This mode of operation is automatical y engaged in DCM and
SR Static Pull-Down
disabled once the converter moves to continuous conduction mode To ensure that the SR gate is held low when the secondary is not in (CCM). See Figure 8. control, the SYNCHRONOUS RECTIFIER DRIVE pin has a nominal y “ON” device to pull the pin low and reduce any voltage on the SR Rather than detecting the magnetizing ring val ey on the primary gate due to capacitive coupling from the FORWARD pin. side, the peak voltage of the FORWARD pin voltage as it rises above the output voltage level is used to gate secondary requests to initiate
Open SR Protection
the switch “ON” cycle in the primary control er. In order to protect against an open SYNCHRONOUS RECTIFIER DRIVE pin system fault the secondary control er has a protection The secondary control er detects when the control er enters in mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is discontinuous-mode and opens secondary cycle request windows connected to an external FET. At start-up the control er will apply a corresponding to minimum switching voltage across the primary current to the SYNCHRONOUS RECTIFIER DRIVE pin; an internal power switch. threshold will correlate to a capacitance of 100 pF. If the external capacitance on the SYNCHRONOUS RECTIFIER DRIVE pin is below Quasi-Resonant (QR) mode is enabled for 20 µs after DCM is 100 pF the resulting voltage is above the reference voltage, and the detected. QR switching is disabled after 20 µs, at which point device will assume the SYNCHRONOUS RECTIFIER DRIVE pin is switching may occur at any time a secondary request is initiated. “open” and there is no FET to drive. If the pin capacitance detected The secondary control er includes blanking of ~1 µs to prevent false is above 100 pF (the resulting voltage is below the reference voltage), detection of primary “ON” cycle when the FORWARD pin rings below the control er will assume an SR FET is connected. ground. -8147-102816 Request Window PI Output Voltage
FORWARD Pin Voltage Time Primary VDS Time
Figure 8. Intel igent Quasi-Resonant Mode Switching.
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Rev. B 03/19 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description InnoSwitch3-MX Functional Description Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics InSOP-24D Package Drawing Part Ordering Information