Datasheet InnoSwitch3-Pro (Power Integrations) - 6

InnoSwitch3-Pro
conduction of the SR FET while the primary is switching. This protection mode also prevents an output overvoltage condition in the P: Primary Chip event that the primary is reset while the secondary is still in control. S: Secondary Chip Start
Wait and Listen
P: Powered Up, Switching S: Powering Up When the primary resumes switching after initial power-up recovery from an input line voltage fault (UV or OV) or an auto-restart event, it will assume control and require a successful handshake to relinquish control to the secondary control er. P: Auto-Restart S: Powering Up As an additional safety measure the primary will pause for an auto-restart on-time period, t (~82 ms), before switching. During AR t this “wait” time, the primary will “listen” for secondary requests. If it AR(OFF) sees two consecutive secondary requests, separated by ~30 ms, the primary will infer secondary control and begin switching in slave S: Has powered No P: Goes to Auto-Restart Off up within tAR S: Bypass Discharging mode. If no pulses occur during the t “wait” period, the primary AR will begin switching under primary control until handshake pulses are received. Yes tAR
Audible Noise Reduction Engine
P: Switching The InnoSwitch3-Pro features an active audible noise reduction mode S: Sends Handshaking Pulses whereby the control er (via a “frequency skipping” mode of operation) avoids the resonant band (where the mechanical structure of the power supply is most likely to resonate − increasing noise amplitude) between 5 kHz and 12 kHz - 200 ms and 83 ms. If a secondary P: Has Received No P: Continuous Switching control er switch request occurs within this time window from the last Handshaking S: Doesn’t Take Control conduction cycle, the gate drive to the power switch is inhibited. Pulses
Secondary Controller
Yes As shown in the block diagram in Figure 4, the IC is powered through P: Stops Switching, Hands regulator 4.4 V block by either VOUT or FW connections to the Over Control to Secondary SECONDARY BYPASS pin. The SECONDARY BYPASS pin is connected to an external decoupling capacitor and fed internal y from the regulator block. The FORWARD pin also connects to the negative edge detection S: Has Taken No P: Not Switching block used for both handshaking and timing to turn on the SR FET Control? S: Doesn’t Take Control connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The FORWARD pin is used to sense when to turn off the SR FET in Yes discontinuous mode operation when the voltage across the FET on resistance drops below the V threshold. SR(TH) End of Handshaking, Secondary Control Mode In continuous conduction mode (CCM) operation of the SR FET is turned off when the feedback pulse is sent to demand the next PI-8876-110818 switching cycle, providing excel ent synchronous operation, free of any overlap for the FET turn-off while operating in continuous mode. Figure 7. Primary-Secondary Handshake Flow Chart. The output voltage is regulated on the VOUT pin and defaults to 5 V at start-up. the secondary detects that the primary is providing more cycles than were requested. The external current sense resistor connected between ISENSE and SECONDARY GROUND pins regulates the output current in constant The most likely event that could require an additional handshake is current regulator mode. when the primary stops switching as the result of a momentary line
Programmable Voltage and Current
brown-out event. When the primary resumes operation, it will default The operating voltage and current set points are set ful y program- to a start-up condition and attempt to detect handshake pulses from mable through I2C interface. The output voltage is fully user the secondary. programmable with a range from 3 V to 24 V. The fast response If secondary does not detect that the primary responds to switching requests for 8 consecutive cycles, or if the secondary detects that the primary is switching without cycle requests for 4 or more consecutive cycles, the secondary control er will initiate a second handshake sequence. This provides additional protection against cross-
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Rev. G 07/19 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description InnoSwitch3-Pro Functional Description Primary Controller Secondary Controller Register Definition Command Registers Telemetry (Read-back) Registers I2C Connection I2C Example Waveforms Applications Example Key application Considerations Selection of Components Components for InnoSwitch3-Pro IC Primary-Side Circuit Components for InnoSwitch3-PRO Secondary-Side Circuit Recommendations for Circuit Board Layout Layout Example Recommendations for Transformer Design Application Considerations for INN3379C and INN3370C Only Quick Design Checklist Theremal Resistance Test Conditions for INN3379C and INN3370C Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Curves InSOP-24D Package Drawing Part Ordering Table MSL Table ESD and Latch-Up Table Part Ordering Information