Datasheet AIS2DW12 (STMicroelectronics) - 10

Block diagram and pin description AIS2DW12 Table 3. Internal pull-up values (typ.) for SDO/SA0 and CS pins Resistor value for SDO/SA0 and CS pins Vdd_IO Typ. (k
Ω
)
1.7 V 54.4 1.8 V 49.2 2.5 V 30.4 3.6 V 20.4 10/60 DocID031240 Rev 4 Document Outline Table 1. Device summary 1 Block diagram and pin description 1.1 Block diagram Figure 1. Block diagram 1.2 Pin description Figure 2. Pin connections Table 2. Pin description Table 3. Internal pull-up values (typ.) for SDO/SA0 and CS pins 2 Mechanical and electrical specifications 2.1 Mechanical characteristics Table 4. Mechanical characteristics @ Vdd = 3.0 V, T = -40°C to +85°C unless otherwise noted 2.2 Electrical characteristics Table 5. Electrical characteristics @ Vdd = 3.0 V, T = -40°C to +85°C unless otherwise noted 2.3 Temperature sensor characteristics Table 6. Temperature sensor characteristics 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Table 7. SPI slave timing values Figure 3. SPI slave timing diagram 2.4.2 I²C - inter-IC control interface Table 8. I²C slave timing values Figure 4. I²C slave timing diagram Table 9. I²C high-speed mode specifications at 1 MHz and 3.4 MHz 2.5 Absolute maximum ratings Table 10. Absolute maximum ratings 3 Terminology and functionality 3.1 Terminology 3.1.1 Sensitivity 3.1.2 Zero-g level offset 3.2 Functionality 3.2.1 Operating modes Table 11. Operating modes 3.2.2 Single data conversion on-demand mode Figure 5. Single data conversion on demand functionality 3.2.3 Self-test 3.2.4 Activity/Inactivity, stationary/motion detection functions 3.2.5 Offset management 3.3 Sensing element 3.4 IC interface 3.5 Factory calibration 3.6 Temperature sensor 4 Application hints Figure 6. AIS2DW12 electrical connections (top view) Table 12. Internal pin status 5 Digital main blocks 5.1 Block diagram of filters Figure 7. Accelerometer chain 5.2 FIFO 5.2.1 Bypass mode 5.2.2 FIFO mode 5.2.3 Continuous mode 5.2.4 Continuous-to-FIFO mode Figure 8. Continuous-to-FIFO mode Figure 9. Trigger event to FIFO for Continuous-to-FIFO mode 5.2.5 Bypass-to-Continuous mode Figure 10. Bypass-to-Continuous mode Figure 11. Trigger event to FIFO for Bypass-to-Continuous mode 6 Digital interfaces Table 13. Serial interface pin description 6.1 I²C serial interface Table 14. I²C terminology 6.1.1 I2C operation Table 15. SAD+Read/Write patterns Table 16. Transfer when master is writing one byte to slave Table 17. Transfer when master is writing multiple bytes to slave Table 18. Transfer when master is receiving (reading) one byte of data from slave Table 19. Transfer when master is receiving (reading) multiple bytes of data from slave 6.2 SPI bus interface Figure 12. Read and write protocol 6.2.1 SPI read Figure 13. SPI read protocol Figure 14. Multiple byte SPI read protocol (2-byte example) 6.2.2 SPI write Figure 15. SPI write protocol Figure 16. Multiple byte SPI write protocol (2-byte example) 6.2.3 SPI read in 3-wire mode Figure 17. SPI read protocol in 3-wire mode 7 Register mapping Table 20. Register map 8 Register description 8.1 OUT_T_L (0Dh) Table 21. OUT_T_L register Table 22. OUT_T_L register description 8.2 OUT_T_H (0Eh) Table 23. OUT_T_H register Table 24. OUT_T_H register description 8.3 WHO_AM_I (0Fh) Table 25. WHO_AM_I register default values 8.4 CTRL1 (20h) Table 26. Control register 1 Table 27. Control register 1 description Table 28. Data rate configuration Table 29. Operating mode selection Table 30. Power mode selection 8.5 CTRL2 (21h) Table 31. Control register 2 Table 32. Control register 2 description 8.6 CTRL3 (22h) Table 33. Control register 3 Table 34. Control register 3 description Table 35. Self-test mode selection 8.7 CTRL4_INT1 (23h) Table 36. Control register 4 Table 37. Control register 4 description 8.8 CTRL5_INT2 (24h) Table 38. Control register 5 Table 39. Control register 5 description 8.9 CTRL6 (25h) Table 40. Control register 6 Table 41. Control register 6 description Table 42. Digital filtering cutoff selection (FDS bit set to ‘0’) Table 43. LPF1 cutoff (FDS bit set to '0') Table 44. Digital high-pass filter cutoff selection (FDS bit set to ‘1’) Table 45. Full-scale selection 8.10 OUT_T (26h) Table 46. OUT_T register Table 47. OUT_T register description 8.11 STATUS (27h) Table 48. STATUS register Table 49. STATUS register description 8.12 OUT_X_L (28h) Table 50. OUT_X_L register 8.13 OUT_X_H (29h) Table 51. OUT_X_H register 8.14 OUT_Y_L (2Ah) Table 52. OUT_Y_L register 8.15 OUT_Y_H (2Bh) Table 53. OUT_Y_H register 8.16 OUT_Z_L (2Ch) Table 54. OUT_Z_L register 8.17 OUT_Z_H (2Dh) Table 55. OUT_Z_H register 8.18 FIFO_CTRL (2Eh) Table 56. FIFO_CTRL register Table 57. FIFO_CTRL register description Table 58. FIFO mode selection 8.19 FIFO_SAMPLES (2Fh) Table 59. FIFO_SAMPLES register Table 60. FIFO_SAMPLES register description 8.20 SIXD_THS (30h) Table 61. SIXD_THS register Table 62. SIXD_THS register description Table 63. 4D/6D threshold setting FS @ ±2 g 8.21 WAKE_UP_THS (34h) Table 64. WAKE_UP_THS register Table 65. WAKE_UP_THS register description 8.22 WAKE_UP_DUR (35h) Table 66. WAKE_UP_DUR register Table 67. WAKE_UP_DUR register description 8.23 FREE_FALL (36h) Table 68. FREE_FALL register Table 69. FREE_FALL register description Table 70. FREE_FALL threshold decoding @ ±2 g FS 8.24 STATUS_DUP (37h) Table 71. STATUS_DUP register Table 72. STATUS_DUP register description 8.25 WAKE_UP_SRC (38h) Table 73. WAKE_UP_SRC register Table 74. WAKE_UP_SRC register description 8.26 SIXD_SRC (3Ah) Table 75. SIXD_SRC register Table 76. SIXD_SRC register description 8.27 ALL_INT_SRC (3Bh) Table 77. ALL_INT_SRC register Table 78. ALL_INT_SRC register description 8.28 X_OFS_USR (3Ch) Table 79. X_OFS_USR register Table 80. X_OFS_USR register description 8.29 Y_OFS_USR (3Dh) Table 81. Y_OFS_USR register Table 82. Y_OFS_USR register description 8.30 Z_OFS_USR (3Eh) Table 83. Z_OFS_USR register Table 84. Z_OFS_USR register description 8.31 CTRL7 (3Fh) Table 85. CTRL7 register Table 86. CTRL7 register description 9 Package information 9.1 Soldering information 9.2 LGA-12 package information Figure 18. LGA-12 2.0 x 2.0 x 0.93 mm package outline and mechanical data 9.3 LGA-12 packing information Figure 19. Carrier tape information for LGA-12 package Figure 20. LGA-12 package orientation in carrier tape Figure 21. Reel information for carrier tape of LGA-12 package Table 87. Reel dimensions for carrier tape of LGA-12 package 10 Revision history Table 88. Document revision history