Datasheet ADA8282 (Analog Devices) - 5

HerstellerAnalog Devices
BeschreibungRadar Receive Path AFE: 4-Channel LNA and PGA
Seiten / Seite21 / 5 — Data Sheet. ADA8282. ABSOLUTE MAXIMUM RATINGS. THERMAL RESISTANCE. Table …
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DokumentenspracheEnglisch

Data Sheet. ADA8282. ABSOLUTE MAXIMUM RATINGS. THERMAL RESISTANCE. Table 3. Parameter Rating. Table 4. Thermal Resistance

Data Sheet ADA8282 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3 Parameter Rating Table 4 Thermal Resistance

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Data Sheet ADA8282 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3.
θ
Parameter Rating
JA is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. Electrical AVDD to EPAD −0.3 V to +3.9 V
Table 4. Thermal Resistance
+INx, −INx, SCLK, SDI, SDO, CS, VIO, RESET, −0.3V to AVDD +
Package Type θJA θJC Unit
−OUTx, +OUTx to EPAD 0.3 V 32-Lead, 5 mm × 5 mm LFCSP 33.51 4.1 °C/W ESD Ratings Human Body Model (HBM) ±4000 V Charged Device Model (CDM) ±2000 V
ESD CAUTION
Environmental Operating Temperature Range (Ambient) −40°C to +125°C Storage Temperature Range (Ambient) −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 5 of 21 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS DIGITAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION RADAR RECEIVE PATH AFE DEFAULT SPI SETTINGS INPUT IMPEDANCE POWER MODES PROGRAMMABLE GAIN RANGE OUTPUT SWING VARIATION WITH GAIN OFFSET VOLTAGE ADJUSTMENTS VIO Pin SINGLE-ENDED OR DIFFERENTIAL INPUT SHORT-CIRCUIT CURRENTS SPI INTERFACE CHANNEL TO CHANNEL PHASE MATCHING APPLICATIONS INFORMATION INCREASED GAIN USING TWO ADA8282 DEVICES IN SERIES MULTIPLEXING INPUTS USING MULTIPLE ADA8282 DEVICES BASIC CONNECTIONS FOR A TYPICAL APPLICATION REGISTER MAP REGISTER SUMMARY REGISTER DETAILS Register 0x00: Interface Configuration Register Register 0x01: Soft Reset Register Register 0x04: Chip ID Low Register Register 0x05: Chip ID High Register Register 0x06: Revision Register Register 0x10: LNA Offset 0 Register Register 0x11: LNA Offset 1 Register Register 0x12: LNA Offset 2 Register Register 0x13: LNA Offset 3 Register Register 0x14: PGA Bias Register Register 0x15: PGA Gain Register Register 0x17: Enable Channel Register Register 0x18: Enable Bias Generator Register Register 0x1D: GPIO Write Register Register 0x1E: GPIO Read Register OUTLINE DIMENSIONS ORDERING GUIDE AUTOMOTIVE PRODUCTS