Datasheet ADRF6516 (Analog Devices) - 4

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ADRF6516 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
IMD3 f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite output voltage Gain = 5 dB 61 dBc Gain = 35 dB 42.5 dBc IMD3 with Input CW Blocker f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite 40 dBc output, gain = 5 dB; blocker at 5 MHz, 10 dBc relative to two-tone composite output voltage Corner Frequency = 31 MHz Output Noise Density Midband, gain = 0 dB −143.5 dBV/√Hz Midband, gain = 20 dB −139 dBV/√Hz Midband, gain = 40 dB −125 dBV/√Hz Second Harmonic, HD2 8 MHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 68 dBc Gain = 40 dB 70 dBc Third Harmonic, HD3 8 MHz fundamental, 1.5 V p-p output voltage Gain = 5 dB 55 dBc Gain = 40 dB 75 dBc IMD3 f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite output voltage Gain = 5 dB 55 dBc Gain = 35 dB 77.5 dBc IMD3 with Input CW Blocker f1 = 14 MHz, f2 = 15 MHz, 1.5 V p-p composite 55 dBc output, gain = 5 dB; blocker at 150 MHz, 10 dBc relative to two-tone composite output voltage DIGITAL LOGIC LE, CLK, DATA, SDO, OFDS pins Input High Voltage, VINH >2 V Input Low Voltage, VINL <0.8 V Input Current, IINH/IINL <1 µA Input Capacitance, CIN 2 pF SPI TIMING LE, CLK, DATA, SDO pins (see Figure 2 and Figure 3) fSCLK 1/tSCLK 20 MHz tDH DATA hold time 5 ns tDS DATA setup time 5 ns tLH LE hold time 5 ns tLS LE setup time 5 ns tPW CLK high pulse width 5 ns tD CLK to SDO delay 5 ns POWER AND ENABLE VPS, VPSD, COM, COMD, ENBL pins Supply Voltage Range 3.15 3.3 3.45 V Total Supply Current ENBL = 3.3 V Corner frequency = 31 MHz 360 mA Corner frequency = 1 MHz 330 mA Disable Current ENBL = 0 V 9 mA Disable Threshold 1.6 V Enable Response Time Delay following ENBL low-to-high transition 20 µs Disable Response Time Delay following ENBL high-to-low transition 300 ns Rev. C | Page 4 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS REGISTER MAP AND CODES THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS AND GAINS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS VALUE ON EVM EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE