Datasheet ADRF6518 (Analog Devices) - 5
| Hersteller | Analog Devices |
| Beschreibung | 1.1 GHz Variable Gain Amplifiers and Baseband Programmable Filters |
| Seiten / Seite | 39 / 5 — Data Sheet. ADRF6518. TIMING DIAGRAMS. tCLK. tPW. CLK. tLH. tLS. tDS. … |
| Revision | A |
| Dateiformat / Größe | PDF / 1.6 Mb |
| Dokumentensprache | Englisch |
Data Sheet. ADRF6518. TIMING DIAGRAMS. tCLK. tPW. CLK. tLH. tLS. tDS. tDH. DATA. WRITE BIT. LSB. LSB + 1. LSB + 2. LSB + 3. MSB – 3. MSB – 2. MSB – 1
Modelllinie für dieses Datenblatt
Textversion des Dokuments
Data Sheet ADRF6518 TIMING DIAGRAMS tCLK tPW CLK tLH tLS LE tDS tDH DATA WRITE BIT LSB LSB + 1 LSB + 2 LSB + 3 MSB – 3 MSB – 2 MSB – 1 MSB - 2 MSB NOTES
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1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 16-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
11449- Figure 2. Write Mode Timing Diagram
t tPW CLK tD CLK tLH tLS LE tDS tDH DATA READ BIT DC DC DC DC DC DC DC DC SDO LSB LSB + 1 LSB + 2 LSB + 3 MSB – 3 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A READ OPERATION, THE FIRST
003
BIT SHOULD BE A LOGIC 0 ON THE DATA LINE. tD SECONDS AFTER THE NEXT FALLING EDGE OF THE CLOCK, DATA ON THE SDO LINE BECOMES VALID AND IS CLOCKED OUT ON THE CONSECUTIVE RISING EDGES OF THE CLOCK
11449- Figure 3. Read Mode Timing Diagram Rev. A | Page 5 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE
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1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE 16-BIT WORD IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
11449- Figure 2. Write Mode Timing Diagram
t tPW CLK tD CLK tLH tLS LE tDS tDH DATA READ BIT DC DC DC DC DC DC DC DC SDO LSB LSB + 1 LSB + 2 LSB + 3 MSB – 3 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL 16-BIT REGISTER. FOR A READ OPERATION, THE FIRST
003
BIT SHOULD BE A LOGIC 0 ON THE DATA LINE. tD SECONDS AFTER THE NEXT FALLING EDGE OF THE CLOCK, DATA ON THE SDO LINE BECOMES VALID AND IS CLOCKED OUT ON THE CONSECUTIVE RISING EDGES OF THE CLOCK
11449- Figure 3. Read Mode Timing Diagram Rev. A | Page 5 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE