AD603Data Sheet4.5V102INPUT GND1V/DIV)100(ΩNCE DA98500mVE P M I UT P96INOUTPUT GND500mV/DIV94 5 8 –500mV 01 100k1M10M100M -01 9- –49ns50ns451ns 9 53 FREQUENCY (Hz) 53 00 00 Figure 19. Input Stage Overload Recovery Time Figure 16. Input Impedance vs. Frequency (Gain = 10 dB) (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope) 1023V)100(ΩINPUT GNDNCE100MV/DIVDA98E P M I1VUT P96OUTPUT GNDIN1V/DIV94 6 01 100k1M10M100M 9- 53 FREQUENCY (Hz) 9 –2V 00 -01 –49ns50ns451ns 9 Figure 17. Input Impedance vs. Frequency (Gain = 30 dB) 53 00 Figure 20. Output Stage Overload Recovery Time (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope) 3.5V1VINPUT100500mV/DIV90GND500mVOUTPUT500mV/DIVGND100% 7 01 1V200ns 9- 53 0 –1.5V 00 -02 –44ns50ns456ns 9 Figure 18. Gain Control Channel Response Time 53 00 Figure 21. Transient Response, G = 0 dB (Input Is 500 ns Period, 50% Duty-Cycle Square Wave, Output Is Captured Using Tektronix 11402 Digitizing Oscilloscope) Rev. K | Page 8 of 24 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation Noise Performance The Gain Control Interface Programming the Fixed-Gain Amplifier Using Pin Strapping Using the AD603 in Cascade Sequential Mode (Optimal SNR) Parallel Mode (Simplest Gain Control Interface) Low Gain Ripple Mode (Minimum Gain Error) Applications Information A Low Noise AGC Amplifier Caution Evaluation Board Outline Dimensions Ordering Guide