ADL5330Data Sheet40–11530–115OIP3OIP330–12020–12020–12510–125INPUT P1dBINPUT P1dB10–1300–130(dBm/Hz)0–135–10–135R (dBm)R (dBm)WEWEO–10–140FLOOR (dBm/Hz)O–20–140FLOORPEPEOUTPUT P1dBOUTPUT P1dB–20–145NOIS–30–145NOIS–30–150–40–150–40–155–50–15500.20.40.60.81.01.21.400.20.40.60.81.01.21.4VGAIN (V) 05134-009 VGAIN (V) 05134-012 Figure 9. Input Compression Point, Output Compression Point, Figure 12. Input Compression Point, Output Compression Point, OIP3, and Noise Floor vs. VGAIN at 100 MHz OIP3, and Noise Floor vs. VGAIN at 2200 MHz 40–11530–120OIP3OIP330–12020–125INPUT P1dB20–12510–130INPUT P1dB10–1300–1350–135–10–140R (dBm)R (dBm)WEWEOUTPUT P1dBO–10–140FLOOR (dBm/Hz)O–20–145FLOOR (dBm/Hz)PEOUTPUT P1dBPE–20–145NOIS–30–150NOIS–30–150–40–155–40–155–50–16000.20.40.60.81.01.21.400.20.40.60.81.01.21.4VGAIN (V) 05134-010 VGAIN (V) 05134-013 Figure 10. Input Compression Point, Output Compression Point, Figure 13. Input Compression Point, Output Compression Point, OIP3, and Noise Floor vs. VGAIN at 450 MHz OIP3, and Noise Floor vs. VGAIN at 2700 MHz 40–115TT30–120OIP320–125INPUT P1dB10–130(dBm/Hz)0–135R (dBm)2E W O–10–140FLOORPEOUTPUT P1dB–20–145NOIS–30–150–40–155100.20.40.60.81.01.21.4CH1 200mV CH2 100mVM100nsA CH4 2.70VVGAIN (V) 05134-011 T 382.000ns 05134-014 Figure 11. Input Compression Point, Output Compression Point, Figure 14. Step Response of Gain Control Input OIP3, and Noise Floor vs. VGAIN at 900 MHz Rev. B | Page 8 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION BASIC CONNECTIONS RF INPUT/OUTPUT INTERFACE GAIN CONTROL INPUT AUTOMATIC GAIN CONTROL INTERFACING TO AN IQ MODULATOR WCDMA TRANSMIT APPLICATION CDMA2000 TRANSMIT APPLICATION SOLDERING INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE