Datasheet ADL5246 (Analog Devices) - 9
| Hersteller | Analog Devices |
| Beschreibung | 3 GHz Variable Gain LNA with Integrated ½ W Driver Amplifier |
| Seiten / Seite | 36 / 9 — Data Sheet. ADL5246. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. IN2. … |
| Revision | A |
| Dateiformat / Größe | PDF / 1.5 Mb |
| Dokumentensprache | Englisch |
Data Sheet. ADL5246. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. IN2. FOU. VPO. GND. 24 GND. RFIN1. 23 GND. 22 NIC. NIC. 21 RFIN3. TOP VIEW
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Data Sheet ADL5246 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T1 T3 S2 IN2 FOU ND ND ND FOU ND R G RF G VPO G R G 32 31 30 29 28 27 26 25 GND 1 24 GND RFIN1 2 23 GND GND 3 22 NIC ADL5246 NIC 4 21 RFIN3 TOP VIEW NIC 5 20 GND VSW1 6 19 NIC NIC 7 EXPOSED PAD 18 RFOUT2 NIC 8 17 NIC 9 1 10 1 12 13 14 15 16 C C 1 C S1 NI ND NI NI N1 N2 G AI AI VSW VPO G G V V NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PADDLE (EP) MUST BE SOLDERED
002
TO A LOW IMPEDANCE GROUND PLANE.
12233- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 3, 10, 20, 23, 24, GND Ground. The exposed paddle (EP) and ground pins must be soldered to a low impedance ground plane. 25, 27, 29, 31, EP 2 RFIN1 RF Input. This pin requires a dc blocking capacitor. Use a 100 pF capacitor for normal operation. 4, 5, 7, 8, 9, 12, NIC No Internal Connection. These pins are not connected to internal circuitry. The user may optionally solder 14, 17, 19, 22 to a low impedance ground plane for grounding, shielding, and printed circuit board (PCB) trace impedance continuity. 6 VSW1 Bypass Switch Control. Logic low = 0 V, and logic high = 3.3 V. Switch logic is shown in Table 5. 11 VPOS1 Bias for the AMP2 LNA. Connect this pin to the dc supply voltage through an RF choke. 13 VSW1 Bypass Switch Control. Logic low = 0 V, and logic high = 3.3 V. Switch logic is shown in Table 5. 15 VGAIN1 Gain Control for VVA1. The gain control range is 0 V to 3.3 V. 16 VGAIN2 Gain Control VVA2. The gain control range is 0 V to 3.3 V. 18 RFOUT2 RF Output of the Voltage Variable Attenuator (VVA) Block. 21 RFIN3 Driver Amplifier Input. This pin requires a dc blocking capacitor. Use a 100 pF capacitor for normal operation. 26 RFOUT3 Driver Amplifier Output. Connect this pin to a dc supply through an RF choke. 28 VPOS2 Bias for VVA1, VVA2, and the AMP3 Bias Circuit. Connect this pin to the dc supply voltage through an RF choke. 30 RFIN2 RF Input to the VGA Block. 32 RFOUT1 Low Noise Amplifier Output. Connect this pin to a dc supply through an RF choke. Rev. A | Page 9 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION BASIC CONNECTIONS Amplifier 1 (AMP1) Amplifier 2 (AMP2) Amplifier 3 (AMP3) Gain Control Amplifier 3 Matching ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE THERMAL INFORMATION AND RECOMMENDED PCB LAND PATTERN FULL CHAIN OPERATION CONSIDERATIONS EVALUATION BOARD CHARACTERIZATION INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADL5246 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS T1 T3 S2 IN2 FOU ND ND ND FOU ND R G RF G VPO G R G 32 31 30 29 28 27 26 25 GND 1 24 GND RFIN1 2 23 GND GND 3 22 NIC ADL5246 NIC 4 21 RFIN3 TOP VIEW NIC 5 20 GND VSW1 6 19 NIC NIC 7 EXPOSED PAD 18 RFOUT2 NIC 8 17 NIC 9 1 10 1 12 13 14 15 16 C C 1 C S1 NI ND NI NI N1 N2 G AI AI VSW VPO G G V V NOTES 1. NIC = NO INTERNAL CONNECTION. 2. THE EXPOSED PADDLE (EP) MUST BE SOLDERED
002
TO A LOW IMPEDANCE GROUND PLANE.
12233- Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1, 3, 10, 20, 23, 24, GND Ground. The exposed paddle (EP) and ground pins must be soldered to a low impedance ground plane. 25, 27, 29, 31, EP 2 RFIN1 RF Input. This pin requires a dc blocking capacitor. Use a 100 pF capacitor for normal operation. 4, 5, 7, 8, 9, 12, NIC No Internal Connection. These pins are not connected to internal circuitry. The user may optionally solder 14, 17, 19, 22 to a low impedance ground plane for grounding, shielding, and printed circuit board (PCB) trace impedance continuity. 6 VSW1 Bypass Switch Control. Logic low = 0 V, and logic high = 3.3 V. Switch logic is shown in Table 5. 11 VPOS1 Bias for the AMP2 LNA. Connect this pin to the dc supply voltage through an RF choke. 13 VSW1 Bypass Switch Control. Logic low = 0 V, and logic high = 3.3 V. Switch logic is shown in Table 5. 15 VGAIN1 Gain Control for VVA1. The gain control range is 0 V to 3.3 V. 16 VGAIN2 Gain Control VVA2. The gain control range is 0 V to 3.3 V. 18 RFOUT2 RF Output of the Voltage Variable Attenuator (VVA) Block. 21 RFIN3 Driver Amplifier Input. This pin requires a dc blocking capacitor. Use a 100 pF capacitor for normal operation. 26 RFOUT3 Driver Amplifier Output. Connect this pin to a dc supply through an RF choke. 28 VPOS2 Bias for VVA1, VVA2, and the AMP3 Bias Circuit. Connect this pin to the dc supply voltage through an RF choke. 30 RFIN2 RF Input to the VGA Block. 32 RFOUT1 Low Noise Amplifier Output. Connect this pin to a dc supply through an RF choke. Rev. A | Page 9 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION BASIC CONNECTIONS Amplifier 1 (AMP1) Amplifier 2 (AMP2) Amplifier 3 (AMP3) Gain Control Amplifier 3 Matching ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE THERMAL INFORMATION AND RECOMMENDED PCB LAND PATTERN FULL CHAIN OPERATION CONSIDERATIONS EVALUATION BOARD CHARACTERIZATION INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE