Datasheet ADW12001 (Analog Devices) - 10

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ADW12001 Pin No. Mnemonic Description
29, 41, 52 DRVDD Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF capacitor in parallel with 10 μF capacitor. 39 OTR_B Out-of-Range Indicator for Channel B. 42 to 51 D0_A (LSB) to D9_A Channel A Data Output Bits. 54 to 56 D10_A to D12_A Channel A Data Output Bits. 57 D13_A (MSB) Channel A Data Output Bits. 58 OTR_A Out-of-Range Indicator for Channel A. 59 OEB_A Output Enable Pin for Channel A. Logic 0 enables Data Bus A. Logic 1 sets outputs to high-Z. 60 PDWN_A Power-Down Function Selection for Channel A. Logic 0 enables Channel A. Logic 1 powers down Channel A (outputs static, not high-Z). 61 MUX_SELECT Data Multiplexed Mode. See Data Format section for how to enable; high setting disables output data multiplexed mode. 62 SHARED_REF Shared Reference Control Pin. Low for independent reference mode, high for shared reference mode. 63 CLK_A Clock Input Pin for Channel A. EP Exposed Pad. This part has an exposed pad on the underside of the package that must be connected to PCB GND. Rev. 0 | Page 10 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE