Datasheet AD9273 (Analog Devices)

Octal LNA/VGA/AAF/ADC and Crosspoint Switch AD9273 FEATURES FUNCTIONAL BLOCK DIAGRAM 8 channels of LNA, VGA, AAF, and ADC N Y DD DD1 DD2 W B Low noise preamplifier (LNA) AV AV PD ST DRV Input-referred noise voltage = 1.26 nV/√Hz LOSW-A (gain = 21.3 dB) @ 5 MHz typical AD9273 LO-A SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB LI-A 12-BIT DOUTA+ LNA SERIAL VGA Single-ended input; V LG-A ADC LVDS IN maximum = 733 mV p-p/ DOUTA– AAF 550 mV p-p/367 mV p-p LOSW-B LO-B Dual-mode active input impedance matching LI-B 12-BIT SERIAL DOUTB+ Bandwidth (BW) > 100 MHz LNA VGA LG-B ADC LVDS DOUTB– AAF Full-scale (FS) output = 4.4 V p-p differential LOSW-C Variable gain amplifier (VGA) LO-C LI-C 12-BIT DOUTC+ Attenuator range = −42 dB to 0 dB LNA SERIAL VGA LG-C ADC LVDS DOUTC– AAF SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB LOSW-D Linear-in-dB gain control LO-D Antialiasing filter (AAF) LI-D 12-BIT DOUTD+ LNA SERIAL VGA LG-D ADC LVDS DOUTD– Programmable 2nd-order low-pass filter (LPF) from AAF LOSW-E 8 MHz to 18 MHz LO-E Programmable high-pass filter (HPF) LI-E 12-BIT DOUTE+ LNA SERIAL VGA LG-E ADC LVDS DOUTE– Analog-to-digital converter (ADC) AAF LOSW-F 12 bits at 10 MSPS to 50 MSPS LO-F SNR = 70 dB LI-F 12-BIT DOUTF+ LNA SERIAL VGA SFDR = 75 dB LG-F ADC LVDS DOUTF– AAF LOSW-G Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) LO-G Data and frame clock outputs LI-G 12-BIT DOUTG+ LNA SERIAL VGA Includes an 8 × 8 differential crosspoint switch to support LG-G ADC LVDS DOUTG– AAF continuous wave (CW) Doppler LOSW-H LO-H Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) LI-H 12-BIT SERIAL DOUTH+ 70 mW per channel in CW Doppler LNA VGA LG-H ADC LVDS DOUTH– AAF Flexible power-down modes Overload recovery in <10 ns L IER T A E L FCO+ IA ACE R Fast recovery from low power standby mode, <2 μs IP RF T FCO– RAT SER PO E DAT L 100-lead TQFP and 144-ball BGA REFERENCE DCO+ INT SWITCH MU DCO– ARRAY APPLICATIONS Medical imaging/ultrasound + – + – B K IO 0] EF IN IN AS L K+ K– Automotive radar :0] AND CS 7 7: SD VR SC CL CL GA GA RBI D[ D[
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GENERAL DESCRIPTION CW C
070 Figure 1. The AD9273 is designed for low cost, low power, small size, and The LNA has a single-ended-to-differential gain that is selectable ease of use. It contains eight channels of a low noise preamplifier through the SPI. The LNA input-referred noise voltage is typically (LNA) with a variable gain amplifier (VGA); an antialiasing 1.26 nV/√Hz at a gain of 21.3 dB, and the combined input-referred filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to- noise voltage of the entire channel is 1.42 nV/√Hz at typical digital converter (ADC). gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB Each channel features a variable gain range of 42 dB, a fully LNA gain, the input SNR is about 91 dB. In CW Doppler mode, differential signal path, an active input preamplifier termination, a the LNA output drives a transconductance amp that is switched maximum gain of up to 52 dB, and an ADC with a conversion through an 8 × 8 differential crosspoint switch. The switch is rate of up to 50 MSPS. The channel is optimized for dynamic programmable through the SPI. performance and low power in applications where a small package size is critical.
Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY PRODUCT HIGHLIGHTS SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Recommendation Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Crosspoint Switch TGC OPERATION Variable Gain Amplifier Gain Control VGA Noise Antialiasing Filter ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE Caution RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE