Datasheet AD9277 (Analog Devices) - 3

AD9277 GENERAL DESCRIPTION
The AD9277 is designed for low cost, low power, small size, The ADC automatically multiplies the sample rate clock for and ease of use. It contains eight channels of a variable gain the appropriate LVDS serial data rate. A data clock (DCO±) for amplifier (VGA) with a low noise preamplifier (LNA); an anti- capturing data on the output and a frame clock (FCO±) trigger aliasing filter (AAF); a 14-bit, 10 MSPS to 50 MSPS analog-to- for signaling a new output byte are provided. digital converter (ADC); and an I/Q demodulator with Powering down individual channels is supported to increase programmable phase rotation. battery life for portable applications. A standby mode option Each channel features a variable gain range of 42 dB, a fully differ- allows quick power-up for power cycling. In CW Doppler opera- ential signal path, an active input preamplifier termination, a tion, the VGA, AAF, and ADC are powered down. The power of maximum gain of up to 52 dB, and an ADC with a conversion the TGC path scales with selectable ADC speed power modes. rate of up to 50 MSPS. The channel is optimized for dynamic The ADC contains several features designed to maximize flexibility performance and low power in applications where a small and minimize system cost, such as a programmable clock, data package size is critical. alignment, and programmable digital test pattern generation. The The LNA has a single-ended-to-differential gain that is selectable digital test patterns include built-in fixed patterns, built-in pseudo- through the SPI. The LNA input noise is typically 0.75 nV/√Hz random patterns, and custom user-defined test patterns entered at a gain of 21.3 dB, and the combined input-referred noise of via the serial port interface. the entire channel is 0.85 nV/√Hz at maximum gain. Assuming Fabricated in an advanced CMOS process, the AD9277 is a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the available in a 16 mm × 16 mm, RoHS compliant, 100-lead input SNR is roughly 92 dB. In CW Doppler mode, each LNA TQFP. It is specified over the industrial temperature range output drives an I/Q demodulator. Each demodulator has inde- of −40°C to +85°C. pendently programmable phase rotation through the SPI with 16 phase settings. The AD9277 requires a LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. Rev. 0 | Page 3 of 48 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE