Datasheet AD9650-EP (Analog Devices) - 10

AD9650-EP Data Sheet Pin No. Mnemonic Type Description
Digital Outputs 7 D0+ Output Channel A/Channel B LVDS Output Data 0—True (LSB). 6 D0− Output Channel A/Channel B LVDS Output Data 0—Complement (LSB). 9 D1+ Output Channel A/Channel B LVDS Output Data 1—True. 8 D1− Output Channel A/Channel B LVDS Output Data 1—Complement. 11 D2+ Output Channel A/Channel B LVDS Output Data 2—True. 10 D2− Output Channel A/Channel B LVDS Output Data 2—Complement. 14 D3+ Output Channel A/Channel B LVDS Output Data 3—True. 13 D3− Output Channel A/Channel B LVDS Output Data 3—Complement. 16 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 15 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 18 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 17 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 24 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 23 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 27 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 26 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 29 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 28 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 33 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 32 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 36 D10+ Output Channel A/Channel B LVDS Output Data 10—True. 35 D10− Output Channel A/Channel B LVDS Output Data 10—Complement. 38 D11+ Output Channel A/Channel B LVDS Output Data 11—True. 37 D11− Output Channel A/Channel B LVDS Output Data 11—Complement. 44 D12+ Output Channel A/Channel B LVDS Output Data 12—True. 43 D12− Output Channel A/Channel B LVDS Output Data 12—Complement. 46 D13+ Output Channel A/Channel B LVDS Output Data 13—True. 45 D13− Output Channel A/Channel B LVDS Output Data 13—Complement. 49 D14+ Output Channel A/Channel B LVDS Output Data 14—True. 48 D14− Output Channel A/Channel B LVDS Output Data 14—Complement. 51 D15+ Output Channel A/Channel B LVDS Output Data 15—True (MSB). 50 D15− Output Channel A/Channel B LVDS Output Data 15—Complement (MSB). 53 OR+ Output Channel A/Channel B LVDS Overrange Output—True. 52 OR− Output Channel A/Channel B LVDS Overrange Output—Complement. 31 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 30 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 55 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. 54 SDIO/DCS Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. 56 CSB Input SPI Chip Select (Active Low). ADC Configuration 57 OEB Input Output Enable Input (Active Low) in External Pin Mode. 58 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Do Not Connect 1, 2, 19, 20, 21, 22, DNC N/A Do Not Connect. 39, 40, 41, 42, 59, 60, 61, 62, 79, 80 Rev. 0 | Page 10 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide