Datasheet AD9279 (Analog Devices) - 2
| Hersteller | Analog Devices |
| Beschreibung | Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator |
| Seiten / Seite | 44 / 2 — AD9279. TABLE OF CONTENTS. REVISION HISTORY. 10/10—Revision 0: Initial … |
| Dateiformat / Größe | PDF / 988 Kb |
| Dokumentensprache | Englisch |
AD9279. TABLE OF CONTENTS. REVISION HISTORY. 10/10—Revision 0: Initial Version
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AD9279 TABLE OF CONTENTS
Features .. 1 Equivalent Circuits... 17 General Description ... 1 Ultrasound Theory of Operation ... 19 Functional Block Diagram .. 1 Channel Overview.. 20 Revision History ... 2 TGC Operation... 20 Specifications... 3 CW Doppler Operation... 33 AC Specifications.. 3 Serial Port Interface (SPI).. 37 Digital Specifications ... 6 Hardware Interface... 37 Switching Specifications .. 7 Memory Map .. 39 ADC Timing Diagrams ... 8 Reading the Memory Map Table.. 39 Absolute Maximum Ratings.. 9 Reserved Locations .. 39 Thermal Impedance ... 9 Default Values ... 39 ESD Caution.. 9 Logic Levels... 39 Pin Configuration and Function Descriptions... 10 Outline Dimensions ... 43 Typical Performance Characteristics ... 13 Ordering Guide .. 43 TGC Mode... 13 CW Doppler Mode... 16
REVISION HISTORY 10/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE
AD9279 TABLE OF CONTENTS
Features .. 1 Equivalent Circuits... 17 General Description ... 1 Ultrasound Theory of Operation ... 19 Functional Block Diagram .. 1 Channel Overview.. 20 Revision History ... 2 TGC Operation... 20 Specifications... 3 CW Doppler Operation... 33 AC Specifications.. 3 Serial Port Interface (SPI).. 37 Digital Specifications ... 6 Hardware Interface... 37 Switching Specifications .. 7 Memory Map .. 39 ADC Timing Diagrams ... 8 Reading the Memory Map Table.. 39 Absolute Maximum Ratings.. 9 Reserved Locations .. 39 Thermal Impedance ... 9 Default Values ... 39 ESD Caution.. 9 Logic Levels... 39 Pin Configuration and Function Descriptions... 10 Outline Dimensions ... 43 Typical Performance Characteristics ... 13 Ordering Guide .. 43 TGC Mode... 13 CW Doppler Mode... 16
REVISION HISTORY 10/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 44 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS ULTRASOUND THEORY OF OPERATION CHANNEL OVERVIEW TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS OUTLINE DIMENSIONS ORDERING GUIDE