Datasheet AD8283 (Analog Devices) - 8

AD8283 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V V R R DD33D 1 DD33D 1 NC DV NC NC D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D DV NC 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 NC 1 54 NC PIN 1 DSYNC 2 INDICATOR 53 TEST4 PDWN 3 52 DVDD18CLK DVDD18 4 51 CLK+ SCLK 5 50 CLK– SDIO 6 49 DVDD33CLK CS 7 48 AVDD33REF AUX 8 47 VREF MUXA 9 AD8283 46 RBIAS ZSEL 10 (TOP VIEW) 45 BAND TEST1 11 44 APOUT TEST2 12 43 ANOUT DVDD33SPI 13 42 TEST3 AVDD18 14 41 AVDD18ADC AVDD33A 15 40 AVDD18 INA– 16 39 INADC+ INA+ 17 38 INADC– NC 18 37 NC 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 – + NC NC F– F+ NC INB– INB+ INC– INC+ IND– IND+ INE INE IN IN DD33B DD33C DD33D DD33E DD33F AV AV AV AV AV NOTES
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1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE SHOULD BE TIED TO ANALOG/DIGITAL GROUND PLANE.
09795- Figure 3.
Table 6. Pin Function Descriptions Pin No. Name Description
0 GND Ground. Exposed paddle on the bottom side; should be tied to the analog/digital ground plane. 1 NC No Connection. Pin can be tied to any potential. 2 DSYNC Data Out Synchronization. 3 PDWN Full Power-Down. Logic high overrides SPI and powers down the part, logic low allows selection through SPI. 4 DVDD18 1.8 V Digital Supply. 5 SCLK Serial Clock. 6 SDIO Serial Data Input/Output. 7 CS Chip Select Bar. 8 AUX Logic high forces to Channel ADC (INADC+/INADC−); AUX has a higher priority than MUXA. 9 MUXA Logic high forces to Channel A unless AUX is asserted. 10 ZSEL Input Impedance Select. Logic high overrides SPI and sets it to 200 kΩ; logic low allows selection through SPI. 11 TEST1 Pin should not be used; tie to ground. 12 TEST2 Pin should not be used; tie to ground. 13 DVDD33SPI 3.3 V Digital Supply, SPI Port. 14 AVDD18 1.8 V Analog Supply. 15 AVDD33A 3.3 V Analog Supply, Channel A. 16 INA− Negative LNA Analog Input for Channel A. 17 INA+ Positive LNA Analog Input for Channel A. 18 NC No Connect. Pin can be tied to any potential. 19 NC No Connect. Pin can be tied to any potential. 20 NC No Connect. Pin can be tied to any potential. 21 AVDD33B 3.3 V Analog Supply, Channel B. 22 INB− Negative LNA Analog Input for Channel B. 23 INB+ Positive LNA Analog Input for Channel B. 24 AVDD33C 3.3 V Analog Supply, Channel C. 25 INC− Negative LNA Analog Input for Channel C. 26 INC+ Positive LNA Analog Input for Channel C. Rev. C | Page 8 of 27 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDIO Pin SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Serial Peripheral Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Logic Levels Reserved Locations Default Values Application Diagrams Outline Dimensions Ordering Guide Automotive Products