Datasheet AD8283 (Analog Devices) - 4

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AD8283 Data Sheet AD8283W Parameter1 Conditions Min Typ Max Unit
ADC Resolution 12 Bits Max Sample Rate 72 MSPS Signal-to-Noise Ratio (SNR) fIN = 1 MHz 68.5 dB Signal-to-Noise and Distortion 66 dB (SINAD) SNRFS 68 dB Differential Nonlinearity (DNL) Guaranteed no missing codes 1 LSB Integral Nonlinearity (INL) 10 LSB Effective Number of Bits (ENOB) 10.67 LSB ADC Output Characteristics Maximum Cap Load Per bit 20 pF IDVDD33 Peak Current with Cap Load Peak current per bit when driving a 40 mA 20 pF load; can be programmed via the SPI port if required ADC REFERENCE Output Voltage Error VREF = 1.024 V ±25 mV Load Regulation At 1.0 mA, VREF = 1.024 V 2 mV Input Resistance 6 kΩ FULL CHANNEL CHARACTERISTICS LNA, PGA, AAF, and ADC SNRFS FIN = 1 MHz Gain = 16 dB 68 dB Gain = 22 dB 68 dB Gain = 28 dB 68 dB Gain = 34 dB 66 dB SINAD FIN = 1 MHz Gain = 16 dB 67 dB Gain = 22 dB 68 dB Gain = 28 dB 67 dB Gain = 34 dB 66 dB SFDR FIN = 1 MHz Gain = 16 dB 68 dB Gain = 22 dB 74 dB Gain = 28 dB 74 dB Gain = 34 dB 73 dB Harmonic Distortion Second Harmonic FIN =1 MHz at −10 dBFS, gain = 16 dB −70 dBc FIN =1 MHz at −10 dBFS, gain = 34 dB −70 dBc Third Harmonic FIN =1 MHz at −10 dBFS, gain = 16 dB −66 dBc FIN =1 MHz at −10 dBFS, gain = 34 dB −75 dBc IM3 Distortion FIN1 = 1 MHz, FIN2 = 1.1 MHz, −1 dBFS, −69 dBc gain = 34 dB Gain Response Time 600 ns Overdrive Recovery Time 200 ns 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. C | Page 4 of 27 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Low Noise Amplifier (LNA) Recommendation Antialiasing Filter (AAF) Mux and Mux Controller ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDIO Pin SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations Serial Peripheral Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Logic Levels Reserved Locations Default Values Application Diagrams Outline Dimensions Ordering Guide Automotive Products