Datasheet AD9648-EP (Analog Devices) - 7
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| Seiten / Seite | 17 / 7 — Enhanced Product. AD9648-EP. Parameter. Temperature Min. Typ. Max. Unit. … |
| Revision | B |
| Dateiformat / Größe | PDF / 309 Kb |
| Dokumentensprache | Englisch |
Enhanced Product. AD9648-EP. Parameter. Temperature Min. Typ. Max. Unit. SWITCHING SPECIFICATIONS. Table 4. Temperature. Min
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Enhanced Product AD9648-EP Parameter Temperature Min Typ Max Unit
DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage I = 50 µA Full 1.79 V OH I = 0.5 mA Full 1.75 V OH Low Level Output Voltage I = 1.6 mA Full 0.2 V OL I = 50 µA Full 0.05 V OL LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (V ), ANSI Mode Full 290 345 400 mV OD Output Offset Voltage (V ), ANSI Mode Full 1.15 1.25 1.35 V OS Differential Output Voltage (V ), Reduced Swing Mode Full 160 200 230 mV OD Output Offset Voltage (V ), Reduced Swing Mode Full 1.15 1.25 1.35 V OS 1 Pul up. 2 Pull down.
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 1000 MHz Conversion Rate1 DCS Enabled Full 20 125 MSPS DCS Disabled Full 10 125 MSPS CLK Period—Divide-by-1 Mode (t ) Full 8 ns CLK CLK Pulse Width High (t ) Full 4 ns CH Aperture Delay (t ) Full 1.0 ns A Aperture Uncertainty (Jitter, t ) Full 0.137 ps rms J DATA OUTPUT PARAMETERS CMOS Mode (DRVDD = 1.8 V) Data Propagation Delay (t ) Full 1.8 2.9 4.4 ns PD DCO Propagation Delay (t )2 Full 2.0 3.1 4.4 ns DCO DCO to Data Skew (t ) Full −1.2 SKEW −0.1 +1.0 ns LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (t ) Full 2.4 ns PD DCO Propagation Delay (t )2 Full 2.4 ns DCO DCO to Data Skew (t ) Full −0.20 SKEW +0.03 +0.25 ns CMOS Mode Pipeline Delay (Latency) Full 16 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 16/16.5 Cycles Wake-Up Time (Power Down)3 Full 350 µs Wake-Up Time (Standby) Full 250 ns Out-of-Range Recovery Time Full 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see the standard AD9648 datasheet). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. B | Page 7 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
Enhanced Product AD9648-EP Parameter Temperature Min Typ Max Unit
DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage I = 50 µA Full 1.79 V OH I = 0.5 mA Full 1.75 V OH Low Level Output Voltage I = 1.6 mA Full 0.2 V OL I = 50 µA Full 0.05 V OL LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (V ), ANSI Mode Full 290 345 400 mV OD Output Offset Voltage (V ), ANSI Mode Full 1.15 1.25 1.35 V OS Differential Output Voltage (V ), Reduced Swing Mode Full 160 200 230 mV OD Output Offset Voltage (V ), Reduced Swing Mode Full 1.15 1.25 1.35 V OS 1 Pul up. 2 Pull down.
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted.
Table 4. Parameter Temperature Min Typ Max Unit
CLOCK INPUT PARAMETERS Input Clock Rate Full 1000 MHz Conversion Rate1 DCS Enabled Full 20 125 MSPS DCS Disabled Full 10 125 MSPS CLK Period—Divide-by-1 Mode (t ) Full 8 ns CLK CLK Pulse Width High (t ) Full 4 ns CH Aperture Delay (t ) Full 1.0 ns A Aperture Uncertainty (Jitter, t ) Full 0.137 ps rms J DATA OUTPUT PARAMETERS CMOS Mode (DRVDD = 1.8 V) Data Propagation Delay (t ) Full 1.8 2.9 4.4 ns PD DCO Propagation Delay (t )2 Full 2.0 3.1 4.4 ns DCO DCO to Data Skew (t ) Full −1.2 SKEW −0.1 +1.0 ns LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (t ) Full 2.4 ns PD DCO Propagation Delay (t )2 Full 2.4 ns DCO DCO to Data Skew (t ) Full −0.20 SKEW +0.03 +0.25 ns CMOS Mode Pipeline Delay (Latency) Full 16 Cycles LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Full 16/16.5 Cycles Wake-Up Time (Power Down)3 Full 350 µs Wake-Up Time (Standby) Full 250 ns Out-of-Range Recovery Time Full 2 Cycles 1 Conversion rate is the clock rate after the divider. 2 Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see the standard AD9648 datasheet). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. Rev. B | Page 7 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE