Datasheet AD9648-EP (Analog Devices) - 4
| Hersteller | Analog Devices |
| Beschreibung | 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter |
| Seiten / Seite | 17 / 4 — AD9648-EP. Enhanced Product. SPECIFICATIONS DC SPECIFICATIONS. Table 1. … |
| Revision | B |
| Dateiformat / Größe | PDF / 309 Kb |
| Dokumentensprache | Englisch |
AD9648-EP. Enhanced Product. SPECIFICATIONS DC SPECIFICATIONS. Table 1. Parameter. Temperature Min. Typ. Max. Unit
Modelllinie für dieses Datenblatt
Textversion des Dokuments
AD9648-EP Enhanced Product SPECIFICATIONS DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 1. Parameter Temperature Min Typ Max Unit
RESOLUTION Full 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −0.8 −0.3 +0.2 % FSR Gain Error Full −6.3 ±1.3 +6.3 % FSR Differential Nonlinearity (DNL)1 Full −0.7 +1.3 LSB 25°C ±0.5 LSB Integral Nonlinearity (INL)1 Full −2.6 +2.6 LSB 25°C ±1.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.01 ±0.8 % FSR Gain Error Full ±0.5 ±7.0 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±50 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.00 1.02 V Load Regulation Error at 1.0 mA Full 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.98 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 V p-p Input Capacitance2 Full 5 pF Input Resistance (Differential) Full 7.5 kΩ Input Common-Mode Voltage Full 0.9 V Input Common-Mode Range Full 0.5 1.3 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current I 1 Full 95 100 mA AVDD I (1.8 V CMOS)1 Full 22.5 23.8 mA DRVDD I (1.8 V LVDS)1 Full 65.0 66.4 mA DRVDD POWER CONSUMPTION DC Input Full 155.5 mW Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) Full 211.5 223 mW Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) Full 288 300 mW Standby Power3 Full 120 mW Power-Down Power Full 2.0 mW 1 Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode). Rev. B | Page 4 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted.
Table 1. Parameter Temperature Min Typ Max Unit
RESOLUTION Full 14 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error Full −0.8 −0.3 +0.2 % FSR Gain Error Full −6.3 ±1.3 +6.3 % FSR Differential Nonlinearity (DNL)1 Full −0.7 +1.3 LSB 25°C ±0.5 LSB Integral Nonlinearity (INL)1 Full −2.6 +2.6 LSB 25°C ±1.0 LSB MATCHING CHARACTERISTIC Offset Error Full ±0.01 ±0.8 % FSR Gain Error Full ±0.5 ±7.0 % FSR TEMPERATURE DRIFT Offset Error Full ±2 ppm/°C Gain Error Full ±50 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 1.00 1.02 V Load Regulation Error at 1.0 mA Full 2 mV INPUT REFERRED NOISE VREF = 1.0 V 25°C 0.98 LSB rms ANALOG INPUT Input Span, VREF = 1.0 V Full 2 V p-p Input Capacitance2 Full 5 pF Input Resistance (Differential) Full 7.5 kΩ Input Common-Mode Voltage Full 0.9 V Input Common-Mode Range Full 0.5 1.3 V POWER SUPPLIES Supply Voltage AVDD Full 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 V Supply Current I 1 Full 95 100 mA AVDD I (1.8 V CMOS)1 Full 22.5 23.8 mA DRVDD I (1.8 V LVDS)1 Full 65.0 66.4 mA DRVDD POWER CONSUMPTION DC Input Full 155.5 mW Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) Full 211.5 223 mW Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) Full 288 300 mW Standby Power3 Full 120 mW Power-Down Power Full 2.0 mW 1 Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. 2 Input capacitance refers to the effective capacitance between one differential input pin and AGND. 3 Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode). Rev. B | Page 4 of 17 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS ORDERING GUIDE