Datasheet AD9257-EP (Analog Devices) - 6

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AD9257-EP Data Sheet SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4. Parameter1, 2 Temp Min Typ Max Unit
CLOCK3 Input Clock Rate Full 10 520 MHz Conversion Rate Full 10 65 MSPS Clock Pulse Width High (tEH) Full 7.69 ns Clock Pulse Width Low (tEL) Full 7.69 ns OUTPUT PARAMETERS3 Propagation Delay (tPD) Full 1.5 2.3 3.1 ns Rise Time (tR) (20% to 80%) Full 300 ps Fall Time (tF) (20% to 80%) Full 300 ps FCO Propagation Delay (tFCO) Full 1.5 2.3 3.1 ns DCO Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/28) ns DCO to Data Delay (tDATA)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/28) − 300 (tSAMPLE/28) (tSAMPLE/28) + 300 ps Data to Data Skew Full ±50 ±200 ps (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) 25°C 35 μs Wake-Up Time (Power-Down)5 25°C 375 μs Pipeline Latency Full 16 Clock cycles APERTURE Aperture Delay (tA) 25°C 1 ns Aperture Uncertainty (Jitter) 25°C 0.1 ps rms Out-of-Range Recovery Time 25°C 1 Clock cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 tSAMPLE/28 is based on the number of bits divided by 2 because the delays are based on half duty cycles. tSAMPLE = 1/fS. 5 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS Table 5. Parameter Description Limit Unit
SYNC TIMING REQUIREMENTS tSSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ tHSYNC SYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS1 See Figure 4 tDS Setup time between the data and the rising edge of SCLK 2 ns min tDH Hold time between the data and the rising edge of SCLK 2 ns min tCLK Period of the SCLK 40 ns min tS Setup time between CSB and SCLK 2 ns min tH Hold time between CSB and SCLK 2 ns min tHIGH SCLK pulse width high 10 ns min tLOW SCLK pulse width low 10 ns min tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK 10 ns min falling edge (not shown in Figure 4) tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK 10 ns min rising edge (not shown in Figure 4) 1 When referring to a single function of a multifunction pin, only the portion of the pin name that is relevant to the specification is listed. For ful pin names of multifunction pins, refer to the Pin Configuration and Function Descriptions section. Rev. A | Page 6 of 13 Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE