Datasheet AD9670 (Analog Devices) - 7

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Data Sheet AD9670 DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C), unless otherwise noted.
Table 2. Parameter1 Temperature Min Typ Max Unit
INPUTS CLK+, CLK−, TX_TRIG+, TX_TRIG− Logic Compliance CMOS/LVDS/LVPECL Differential Input Voltage42 0.2 3.6 V p-p Input Voltage Range GND − 0.2 AVDD1 + 0.2 V Input Common-Mode Voltage 0.9 V Input Resistance (Differential) 25°C 15 kΩ Input Capacitance 25°C 4 pF MLO+, MLO−, RESET+, RESET− Logic Compliance LVDS/LVPECL Differential Input Voltage2 0.250 2 × AVDD2 V p-p Input Voltage Range GND − 0.2 AVDD2 + 0.2 V Input Common-Mode Voltage −0.3 AVDD2/2 +0.3 V Input Resistance (Single-Ended) 25°C 20 kΩ Input Capacitance 25°C 1.5 pF LOGIC INPUTS PDWN, STBY, SCLK, SDIO, ADDRx Logic 1 Voltage 1.2 DRVDD + 0.3 V Logic 0 Voltage 0.3 V Input Resistance3 25°C 30 (26 for SDIO) kΩ Input Capacitance3 25°C 2 (5 for SDIO) pF CSB Logic 1 Voltage 1.2 DRVDD + 0.3 V Logic 0 Voltage 0.3 V Input Resistance 25°C 26 kΩ Input Capacitance 25°C 2 pF LOGIC OUTPUTS SDIO4 Logic 1 Voltage (IOH = 800 μA) 1.79 V Logic 0 Voltage (IOL = 50 μA) 0.05 V GPO0/GPO1/GPO2/GPO3 Logic 0 Voltage (IOL = 50 μA) 0.05 V DIGITAL OUTPUTS (DOUTx+, DOUTx−) ANSI-644 Logic Compliance LVDS Differential Output Voltage (VOD) 247 454 mV Output Offset Voltage (VOS) 1.125 1.375 V Output Coding (Default) Offset binary Low Power, Reduced Signal Option Logic Compliance LVDS Differential Output Voltage (VOD) 150 250 mV Output Offset Voltage (VOS) 1.10 1.30 V Output Coding (Default) Offset binary 1 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 2 Specified for LVDS and LVPECL only. 3 The typical input resistance and input capacitance values deviate for SDIO; these deviations are noted in the Typ column. 4 Specified for 13 SDIO pins sharing the same connection. Rev. A | Page 7 of 52 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ADC Timing Diagram CW Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CHARACTERISTICS CW DOPPLER MODE CHARACTERISTICS THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter Antialiasing Filter/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing Output Zero Stuffing SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter DIGITAL DEMODULATOR/DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband Antialiasing Filter and Decimate by 2 High-Pass Filter BASEBAND DEMODULATOR AND DECIMATOR Numerically Controlled Oscillator Decimation Filter Coefficient Memory DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator Filter Coefficients DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED STARTUP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE