Datasheet AD9674 (Analog Devices) - 6

AD9674 Data Sheet Parameter2 Test Conditions/Comments Min Typ Max Unit
Close In SNR −3 dBFS input, fRF = 2.5 MHz, 156 dBc/√Hz fLO = 40 MHz, 1 kHz offset, 16LO5 mode, one channel enabled −3 dBFS input, fRF = 2.5 MHz, 161 dBc/√Hz fLO = 40 MHz, 1 kHz offset, 16LO5 mode, eight channels enabled Two-Tone Intermodulation Distortion fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, −58 dBc (IMD3) fLO = 80 MHz, ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2 LO Harmonic Rejection −20 dBc Quadrature Phase Error I to Q, all phases, 1 σ 0.15 Degrees I/Q Amplitude Imbalance I to Q, all phases, 1 σ 0.015 dB Channel to Channel Matching Phase I to I, Q to Q, 1 σ 0.5 Degrees Amplitude I to I, Q to Q, 1 σ 0.25 dB POWER SUPPLY Mode I/Mode II/Mode III/Mode IV1, 3 AVDD1 1.7 1.8 1.9 V AVDD2 2.85 3.0 3.6 V DVDD 1.3 1.4 1.9 V DRVDD 1.7 1.8 1.9 V IAVDD1 TGC mode, LO band mode 144/188/224/2943 mA CW Doppler mode 4 mA IAVDD2 TGC mode, no signal, low band mode 230 mA TGC mode, no signal, high band mode 239 mA CW Doppler mode, eight channels 140 mA enabled IDVDD RF decimator enabled in Mode III1 and 47/75/57/913 mA Mode IV,1 digital HPF enabled RF decimator enabled in Mode III1 and 30/48/42/653 mA Mode IV,1 digital HPF disabled IDRVDD ANSI-644 mode 125/170/128/1693 mA Low power (IEEE 1596.3 similar) mode 109/155/114/1543 mA Total Power Dissipation (Including TGC mode, no signal, RF decimator 1190/1385/ 1325/1535/ mW Output Drivers) enabled in Mode III and Mode IV, 1365/16003 1515/17653 digital HPF disabled TGC mode, no signal, RF decimator 1215/1425/ 1350/1575/ mW enabled in Mode III1 and Mode IV, 1 1385/16403 1535/18003 digital HPF enabled CW Doppler mode, eight channels 500 mW enabled Power-Down Dissipation 30 mW Standby Power Dissipation 630 mW ADC Resolution 14 Bits SNR fIN = 5 MHz 75 dB ADC REFERENCE Output Voltage Error VREF = 1 V ±50 mV Load Regulation at 1.0 mA VREF = 1 V 2 mV Input Resistance 7.5 kΩ 1 The ADC speed modes depending on the encoding clock rate. 2 For a complete set of definitions and information about how these tests were completed, see the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation. 3 The slashes mean that the four different power and current values are listed for the four different modes (Mode I, Mode II, Mode III, Mode IV). 4 The overrange condition is specified as 6 dB more than the full-scale input range. 5 The internal LO frequency, fLO, is generated from the supplied multiplier local oscillator frequency, fMLO, by dividing it up by a configurable divider value (M) that can be 4, 8, or 16; the MLO signal is named 4LO, 8LO, or 16LO, accordingly. Rev. A | Page 6 of 47 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagram CW Doppler Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Digital Outputs and Timing Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation DIGITAL RF DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE