Datasheet AD7466-KGD (Analog Devices) - 6
| Hersteller | Analog Devices |
| Beschreibung | 1.6 V Micro-Power 12-Bit ADC |
| Seiten / Seite | 9 / 6 — AD7466-KGD. Known Good Die. TIMING EXAMPLES. Timing Example 2. Timing … |
| Revision | A |
| Dateiformat / Größe | PDF / 177 Kb |
| Dokumentensprache | Englisch |
AD7466-KGD. Known Good Die. TIMING EXAMPLES. Timing Example 2. Timing Example 1. tCONVERT. SCLK. tQUIET. ACQUISITION TIME. AUTOMATIC
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AD7466-KGD Known Good Die TIMING EXAMPLES Timing Example 2
Figure 3 shows some of the timing parameters from Table 2 in The AD7466-KGD can also operate with slower clock frequencies. the Timing Specifications section. As shown in Figure 3, assuming VDD = 1.8 V, fSCLK = 2 MHz, and a
Timing Example 1
throughput of 50 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 20 µs. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 µs = 7.55 µs, As shown in Figure 3, fSCLK = 3.4 MHz and a throughput of and t8 = 60 ns maximum, this leaves tQUIET to be 12.39 µs, which 100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 µs. satisfies the requirement of 10 ns for tQUIET. The part is fully Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns + powered up and the signal is fully acquired at Point A, which 4.41 µs = 4.46 µs, and t8 = 60 ns maximum, then tQUIET = 5.48 µs, means the acquisition/power-up time is t2 + 2(1/fSCLK) = 55 ns + which satisfies the requirement of 10 ns for tQUIET. The part is 1 µs = 1.05 µs, satisfying the maximum requirement of 640 ns fully powered up and the signal is fully acquired at Point A. for the power-up time. In this example and with other slower This means that the acquisition/power-up time is t2 + 2(1/fSCLK) clock values, the part is fully powered up and the signal already = 55 ns + 588 ns = 643 ns, satisfying the maximum requirement acquired before the third SCLK fal ing edge; however, the track- of 640 ns for the power-up time. and-hold does not go into hold mode until that point. In this example, the part can be powered up and the signal can be fully acquired at approximately Point B in Figure 3.
CS tCONVERT t2 B A SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET ACQUISITION TIME AUTOMATIC POWER-DOWN TRACK-AND-HOLD IN TRACK TRACK-AND-HOLD IN HOLD 1/THROUGHPUT
003
POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.
10315- Figure 3. AD7466-KGD Serial Interface Timing Diagram Example Rev. A | Page 6 of 9 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE
AD7466-KGD Known Good Die TIMING EXAMPLES Timing Example 2
Figure 3 shows some of the timing parameters from Table 2 in The AD7466-KGD can also operate with slower clock frequencies. the Timing Specifications section. As shown in Figure 3, assuming VDD = 1.8 V, fSCLK = 2 MHz, and a
Timing Example 1
throughput of 50 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 20 µs. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 µs = 7.55 µs, As shown in Figure 3, fSCLK = 3.4 MHz and a throughput of and t8 = 60 ns maximum, this leaves tQUIET to be 12.39 µs, which 100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 µs. satisfies the requirement of 10 ns for tQUIET. The part is fully Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns + powered up and the signal is fully acquired at Point A, which 4.41 µs = 4.46 µs, and t8 = 60 ns maximum, then tQUIET = 5.48 µs, means the acquisition/power-up time is t2 + 2(1/fSCLK) = 55 ns + which satisfies the requirement of 10 ns for tQUIET. The part is 1 µs = 1.05 µs, satisfying the maximum requirement of 640 ns fully powered up and the signal is fully acquired at Point A. for the power-up time. In this example and with other slower This means that the acquisition/power-up time is t2 + 2(1/fSCLK) clock values, the part is fully powered up and the signal already = 55 ns + 588 ns = 643 ns, satisfying the maximum requirement acquired before the third SCLK fal ing edge; however, the track- of 640 ns for the power-up time. and-hold does not go into hold mode until that point. In this example, the part can be powered up and the signal can be fully acquired at approximately Point B in Figure 3.
CS tCONVERT t2 B A SCLK 1 2 3 4 5 13 14 15 16 t8 tQUIET ACQUISITION TIME AUTOMATIC POWER-DOWN TRACK-AND-HOLD IN TRACK TRACK-AND-HOLD IN HOLD 1/THROUGHPUT
003
POINT A: THE PART IF FULLY POWERED UP WITH VIN FULLY ACQUIRED.
10315- Figure 3. AD7466-KGD Serial Interface Timing Diagram Example Rev. A | Page 6 of 9 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS TIMING EXAMPLES Timing Example 1 Timing Example 2 ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS OUTLINE DIMENSIONS DIE SPECIFICATIONS AND ASSEMBLY RECOMMENDATIONS ORDERING GUIDE