Datasheet ADHV4702-1 (Analog Devices) - 6

link to page 6 link to page 20
ADHV4702-1 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 2. MAXIMUM POWER DISSIPATION Parameter Rating
The maximum safe power dissipation in the package is limited Supply Voltage (VCC to VEE) 225 V by the associated rise in TJ on the die. At approximately 150°C, Output Voltage VCC to VEE which is the glass transition temperature, the plastic begins to Common-Mode Input Voltage VCC to VEE change its properties. Exceeding a TJ of 150°C can result in changes Differential Input Voltage ±2.0 V in the silicon devices, potentially causing failure. Table 3 shows the Input Current ±5 mA junction-to-case thermal resistance (θJC) for the LFCSP. For DGND Voltage VCC − 12 V to VEE more detailed information on power dissipation and thermal Voltage management, see the Applications Information section RESERVED, SD, and TMP Pins DGND to DGND + 6 V
THERMAL RESISTANCE
COMP Pin VCC − 5 V to VCC Thermal performance is directly linked to printed circuit board RADJ Pin DGND to DGND + 0.6 V (PCB) design and operating environment. Careful attention to Storage Temperature Range −65°C to +150°C PCB thermal design is required. Operating Temperature Range −40°C to +85°C Lead Temperature (Soldering 10 sec)1 260°C θJA is the natural convection, junction to ambient thermal resistance Junction Temperature (T measured in a one cubic foot sealed enclosure. θ J) 150°C JC is the junction to case thermal resistance. 1 See IPC/JEDEC J-STD-020 for more information. Stresses at or above those listed under Absolute Maximum
Table 3. Thermal Resistance
Ratings may cause permanent damage to the product. This is a
Package Type θJA θJC Unit
stress rating only; functional operation of the product at these CP-12-81 37 1 °C/W or any other conditions above those indicated in the operational 1 The data is collected from a 2S2P board. A cold plate is attached to the section of this specification is not implied. Operation beyond bottom side of the PCB using 100 µm thermal interface material (TIM) for θJC the maximum operating conditions for extended periods may simulation. See JEDEC standard for additional information. affect product reliability.
ESD CAUTION
Rev. A | Page 6 of 21 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ±12 V TO ±110 V SUPPLY ABSOLUTE MAXIMUM RATINGS MAXIMUM POWER DISSIPATION THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INTERNAL ELECTROSTATIC DISCHARGE (ESD) PROTECTION SLEW BOOST CIRCUIT AND PROTECTION DIGITAL GROUND (DGND) RESISTOR ADJUSTABLE QUIESCENT CURRENT (RADJ) SHUTDOWN PIN (SDB) TEMPERATURE MONITOR (TMP) OVERTEMPERATURE PROTECTION OUTPUT CURRENT DRIVE AND SHORT-CIRCUIT PROTECTION EXTERNAL COMPENSATION AND CAPACITIVE LOAD (CLOAD) DRIVING SAFE OPERATING AREA LFCSP PACKAGE AND HIGH VOLTAGE PIN SPACING EXPOSED PAD (EPAD) APPLICATIONS INFORMATION POWER SUPPLY AND DECOUPLING HIGH VOLTAGE GUARD RING HIGH VOLTAGE DAC VOLTAGE SUBTRACTOR HIGH CURRENT OUTPUT DRIVER SIGNAL RANGE EXTENDER OUTLINE DIMENSIONS ORDERING GUIDE